1 / 20

IP Core Design

IP Core Design. Patrick Longa. Outline. Intellectual Property (IP) Core: basics IP Core classification IP Core standardization Standard buses/interfaces for IP Cores IP Cores in the market Example with FIR Filter Compiler. IP Core: basics. Intellectual Property (IP) core:

cuyler
Download Presentation

IP Core Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. IP Core Design Patrick Longa

  2. Outline • Intellectual Property (IP) Core: basics • IP Core classification • IP Core standardization • Standard buses/interfaces for IP Cores • IP Cores in the market • Example with FIR Filter Compiler

  3. IP Core: basics Intellectual Property (IP) core: “Macro” structures with specific industrial-standard function that can be flexibly be adapted and reused in SoC designs. From “sea of cells” to “sea of hard macros” * Figures extracted from [2].

  4. IP Core classification IP Classification: hard cores and soft cores * Partially extracted from [1].

  5. IP Core standardization VSI Alliance (VSIA)  Open, international organization  Specify standards for IP and reuse in SoC designs  Quality IP (QIP) Metric v2.0 Open Measure of Reuse Excellence (OpenMORE) assessment program  Donated by Mentor Graphics / Synopsys to VSIA  Evaluate the reusability level of hard/soft IP cores Open Core Protocol International Partnership (OCP-IP)  Non-profit organization that promotes the Open Core Protocol (OCP)  Specify standards for IP cores in SoC designs  Payment to have access to specifications Structure for Packaging, Integrating and Re-using IP within Tool-flows (Spirit) Consortium  Create standards for IP interoperability: • Standard for describing IP cores • Standard for creating an IP tool integration API

  6. IP Core standardization Technology-dependent company-based certifications: Altera  SOPC Builder ready AMPP Approved Stamp Xilinx  AllianceCore qualification Lattice  ISPLeverCore Approved

  7. Standard bus/interface for IP Cores Wishbone: created by Silicore • Open bus/interface for IP cores in SoC designs. • Supports 8,16, 32 and 64-bit data bus, synchronous. • Free of charge. Advanced Microcontroller Bus Architecture (AMBA): created by ARM • Supports 32, 64 and 128-bit data bus with 32-bit address bus. • Includes 3 buses: • Advanced High-performance Bus (AHB). • Advanced System Bus (ASB). • Advanced Peripheral Bus (APB). CoreConnect: created by IBM • Supports 32, 64 and 128-bit data bus, extendable to 256 bits. • Includes the next elements: • Procesor Local Bus (PLB). • On-chip Peripeheral Bus (OPB). • A bus bridge. • DCR bus. * Figure extracted from [12].

  8. IP Cores in the market • ALTERA: Altera MegaCore functions and AMPP Megafunctions • Embedded processor cores supported by SOPC Builder •  NIOS, NIOS II, several 16, 8, 4-bit microcontrollers. • Interfaces and peripherals  SRAM memories, interrupt controllers, UARTs, USB, I2C, DMA controllers, PCI, PCI-X buses, Ethernet controllers, LCD and smart card interfaces, etc. • Communications  standard-based communication protocols and interfaces such as UTOPIA, HDLC, Bluetooth, FlexBus, and others. • DSP  supported by DSP Builder tool • Filtering and modulation: FIR, IIR filters, Up-converters, NCOs. • Transforms: FFT, IFFT, DCT and DWT. • Error correction: Reed Solomon encoder/decoder, Viterbi encoder/decoder • Image and Video processing: color space converter, JPEG and JPEG2000 • encoder/decoder.

  9. IP Cores in the market Altera MegaCores and AMPP Megafunctions for DSP

  10. IP Cores in the market XILINX: Xilinx LogicCORE functions and AllianceCORE IP cores Similar IP alternatives in interface / peripherals and Communications. Embedded processor cores supported by Platform Studio  PicoBlaze, MicroBlaze, 16, 8, 4-bit microcontrollers. DSP  supported by System Generator for DSP tool PDSP soft cores Soft processor cores

  11. Example with FIR Filter Compiler Create a new project and open the MegaWizard Plug-In Manager

  12. Example with FIR Filter Compiler Create a new Megafunction unit and select FIR Compiler 3.3.0 from the IP MegaStore

  13. Example with FIR Filter Compiler Options in the IP Toolbench:

  14. Example with FIR Filter Compiler 1.- Parameterize step: New/edit coefficient set Plot options: fixed / floating coefficients, frequency response / time response and coefficients Coefficients bitwidth: 2 to 32 Coefficient scaling Device family Filter structure: fully-serial, fully parallel, multi-bit serial (DA) Pipeline level Data/coefficient storage: logic cells, memory blocks Output/ Input specifications

  15. Example with FIR Filter Compiler Coefficient generator: Rate: single, interpolation, decimation Filter type: low-pass, high-pass, band-pass, band reject. Number of coeficients. Cutoff freq. Sample rate. Window type: rectangular, Hamming, Hanning, Blackman

  16. Example with FIR Filter Compiler

  17. Example with FIR Filter Compiler • 2.- Simulation Step: • Simulation model: • VHDL and Verilog • Quartus II • Matlab M-file generation 3.- Generation Step

  18. Example with FIR Filter Compiler Instantiation Compilation results:

  19. Example with FIR Filter Compiler Simulation results:

  20. References [1] International Technology Roadmap for Semiconductors (ITRS), 2001. [2] “Hard Macros will revolutionize SoC Design”, E. Wein, EE Design, 2004. [3] Virtual Socket Interface Alliance (VSIA), website: www.vsi.org [4] Open Core Protocol International Partnership (OCP-IP), website: www.ocpip.org [5] The Structure for Packaging, Integrating and Re-using IP within Tool-flows (Spirit) Consortium, website: www.spiritconsortium.com [6] Altera Corporation, website: www.altera.com [7] Xilinx Corporation, website: www.xilinx.com [8] Lattice Semiconductor Corporation, website: www.latticesemi.com [9] QuickLogic Corporation, website: www.quicklogic.com [10] OpenCores Project, website: www.opencores.com [11] AMBA Home Page, website: www.arm.com/products/solutions/AMBAHomePage.html [12] CoreConnect Home Page, website: www-03.ibm.com/chips/products/coreconnect/

More Related