IP Core Design. Patrick Longa. Outline. Intellectual Property (IP) Core: basics IP Core classification IP Core standardization Standard buses/interfaces for IP Cores IP Cores in the market Example with FIR Filter Compiler. IP Core: basics. Intellectual Property (IP) core:
Intellectual Property (IP) core:
“Macro” structures with specific industrial-standard function that can be
flexibly be adapted and reused in SoC designs.
From “sea of cells” to “sea of hard macros”
* Figures extracted from .
IP Classification: hard cores and soft cores
* Partially extracted from .
VSI Alliance (VSIA)
Open, international organization
Specify standards for IP and reuse in SoC designs
Quality IP (QIP) Metric v2.0
Open Measure of Reuse Excellence (OpenMORE) assessment program
Donated by Mentor Graphics / Synopsys to VSIA
Evaluate the reusability level of hard/soft IP cores
Open Core Protocol International Partnership (OCP-IP)
Non-profit organization that promotes the Open Core Protocol (OCP)
Specify standards for IP cores in SoC designs
Payment to have access to specifications
Structure for Packaging, Integrating and Re-using IP within Tool-flows (Spirit) Consortium
Create standards for IP interoperability:
Technology-dependent company-based certifications:
Altera SOPC Builder ready
AMPP Approved Stamp
Xilinx AllianceCore qualification
Lattice ISPLeverCore Approved
Wishbone: created by Silicore
Advanced Microcontroller Bus Architecture (AMBA): created by ARM
CoreConnect: created by IBM
extendable to 256 bits.
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Altera MegaCores and AMPP Megafunctions for DSP
XILINX: Xilinx LogicCORE functions and AllianceCORE IP cores
Similar IP alternatives in interface / peripherals and Communications.
Embedded processor cores supported by Platform Studio
PicoBlaze, MicroBlaze, 16, 8, 4-bit microcontrollers.
DSP supported by System Generator for DSP tool
PDSP soft cores
Soft processor cores
Create a new project and open the MegaWizard Plug-In Manager
Create a new Megafunction unit and select FIR Compiler 3.3.0 from the IP MegaStore
Options in the IP Toolbench:
1.- Parameterize step:
New/edit coefficient set
Plot options: fixed / floating coefficients, frequency response / time response and coefficients
Coefficients bitwidth: 2 to 32
Filter structure: fully-serial, fully parallel, multi-bit serial (DA)
Data/coefficient storage: logic cells, memory blocks
Output/ Input specifications
Rate: single, interpolation, decimation
Filter type: low-pass, high-pass, band-pass, band reject.
Number of coeficients.
Window type: rectangular, Hamming, Hanning, Blackman
3.- Generation Step
 International Technology Roadmap for Semiconductors (ITRS), 2001.
 “Hard Macros will revolutionize SoC Design”, E. Wein, EE Design, 2004.
 Virtual Socket Interface Alliance (VSIA), website: www.vsi.org
 Open Core Protocol International Partnership (OCP-IP), website: www.ocpip.org
 The Structure for Packaging, Integrating and Re-using IP within Tool-flows (Spirit) Consortium, website: www.spiritconsortium.com
 Altera Corporation, website: www.altera.com
 Xilinx Corporation, website: www.xilinx.com
 Lattice Semiconductor Corporation, website: www.latticesemi.com
 QuickLogic Corporation, website: www.quicklogic.com
 OpenCores Project, website: www.opencores.com
 AMBA Home Page, website: www.arm.com/products/solutions/AMBAHomePage.html
 CoreConnect Home Page, website: www-03.ibm.com/chips/products/coreconnect/