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EE2420 – Digital Logic Summer II 2013. Set 12: Multiplexers, Decoders, Encoders, Shift Register Class book: Chapter 6 Online book: chapter 8. Hassan Salamy Ingram School of Engineering Texas State University. Multiplexer.

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ee2420 digital logic summer ii 2013
EE2420 – Digital LogicSummer II 2013

Set 12: Multiplexers, Decoders,

Encoders, Shift Register

Class book: Chapter 6

Online book: chapter 8

Hassan Salamy

Ingram School of Engineering

Texas State University

multiplexer
Multiplexer
  • In its standard form, a multiplexer takes an N-bit control input to determine which of 2N data inputs will be passed to its single output.
  • In other words, a multiplexer selects one of multiple inputs
  • Functions may be implemented by using a combination of the control inputs and data inputs.
a 2 to 1 multiplexer
A 2-to-1 multiplexer

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(b) Truth table

(a) Graphical symbol

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(c) Sum-of-products circuit

a 4 to 1 multiplexer
A 4-to-1 multiplexer.

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(a) Graphic symbol

(b) Truth table

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(c) Circuit

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using 2 to 1 multiplexers to build a 4 to 1 multiplexer
Using 2-to-1 multiplexers to build a 4-to-1 multiplexer

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a 16 to 1 multiplexer
A 16-to-1 multiplexer.

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a practical application of multiplexers
A practical application of multiplexers

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(a) A 2x2 crossbar switch

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(b) Implementation using multiplexers

synthesis of a logic function using multiplexers
Synthesis of a logic function using multiplexers

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(a) Implementation using a 4-to-1 multiplexer

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(c) Circuit

(b) Modified truth table

implementation of the three input majority function using a 4 to 1 multiplexer
Implementation of the three-input majority function using a 4-to-1 multiplexer.

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(a) Modified truth table

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three input xor implemented wit 2 to 1 multiplexers
Three-input XOR implemented wit 2-to-1 multiplexers

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(a) Truth table

(b) Circuit

three input xor function implemented with a 4 to 1 multiplexer
Three-input XOR function implemented with a 4-to-1 multiplexer

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(b) Circuit

(a) Truth table

the three input majority function implemented using a 2 to 1 multiplexer
The three-input majority function implemented using a 2-to-1 multiplexer.

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(b) Truth table

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(b) Circuit

what is a demultiplexer demux
What is a Demultiplexer (DEMUX)?

Demultiplexer

Block Diagram

1

2N

Input

(source)

Outputs

(destinations)

N

Select

Lines

DEMUX

  • A DEMUX is a digital switch with a single input (source) and a multiple outputs (destinations).
  • The select lines determine which output the input is connected to.
  • DEMUX Types

 1-to-2 (1 select line)

 1-to-4 (2 select lines)

 1-to-8 (3 select lines)

 1-to-16 (4 select lines)

typical application of a demux
Typical Application of a DEMUX

Multiple Destinations

Single Source

Selector

B/W Laser

Printer

Fax

Machine

Color Inkjet

Printer

D0

D1

D2

D3

Pen

Plotter

X

DEMUX

decoder
Decoder
  • In its standard form, a decoder takes an N-bit input and outputs 2N functions, each of which is active for exactly one input combination.
  • In other words, a decoder outputs the minterms of the inputs (or with inverted outputs, the maxterms)
  • Functions may be implemented with the addition of a single extra gate. For example, an OR gate may be used to combine minterms for a sum-of-products implementation or an AND gate may be used to combine maxterms for a product-of-sums implementation.
an n to 2 n binary decoder
An n-to-2n binary decoder.

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slide17
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(a) Truth table

(b) Graphical symbol

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(c) Logic circuit

A 2-to-4 decoder.

a 3 to 8 decoder using two 2 to 4 decoders
A 3-to-8 decoder using two 2-to-4 decoders.

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slide19
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A 4-to-16 decoder built using a decoder tree.

a 4 to 1 multiplexer built using a decoder
A 4-to-1 multiplexer built using a decoder.

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a 2 m x n read only memory rom block
A 2m x n read-only memory (ROM) block.

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decoder

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a 2 n to n binary encoder
A 2n-to-n binary encoder.

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inputs

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a 4 to 2 binary encoder
A 4-to-2 binary encoder.

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(a) Truth table

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4 bit data shifter
4-bit Data Shifter
  • Data Shifter
    • A combinational logic shifter is a device that produces an output obtained by shifting its input
    • Right Shift: The Most Significant bit is called the fill bit and the Least Significant bit is called the spill bit
    • Left Shift: MSB is the spill bit – LSB is the fill bit
  • Processes:
    • Logical Shift => a logic zero is inserted in the fill position
    • Arithmetic => the sign bit is extended in a right shift
    • End-around [or rotate]
4 bit logical shifter problem statement
4-bit Logical ShifterProblem Statement
  • Step 1: Clear Problem Statement
    • Design and implement a 4-bit logical shifter that has 4-bit input “A”, 4-bit output “S”, and 1-bit controls X and Y where:
4 bit logical shifter conceptualization
4-bit Logical ShifterConceptualization
  • Step 2: Conceptualization
    • This 4-bit shifter can be represented by the black-box model below with the associated Output Table
4 bit logical shifter solution simplification
4-bit Logical Shifter Solution/Simplification
  • Step 3: Solution/Simplification
    • The output table, with it’s different terms and exact duplication of bit values - - Should suggest a multiplexer
    • The logic functions describing the assignment of the values is:
4 bit logical shifter realization and verification
4-bit Logical Shifter Realization and Verification
  • Step 4: Realization
    • Those 4 output values can be implemented using four 4-to-1 mux’s as follows:
  • Step 5: Verification
    • Lab time! - - Does it really do what you designed it to do?
    • Return to that K-map/Truth table and be sure!
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