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Fernando J. Barbosa barbosa@jlab

Fernando J. Barbosa barbosa@jlab.org. F1TDC Status Update Hall D Collaboration Meeting Indiana University – Bloomington, IN May 20-22, 2004. Team Members. Design F. J. Barbosa Ed Jastrzembski James Proffitt Layout Jeff Wilson Production Chris Cuevas Software David Abbott

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Fernando J. Barbosa barbosa@jlab

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  1. Fernando J. Barbosa barbosa@jlab.org F1TDC Status UpdateHall D Collaboration MeetingIndiana University – Bloomington, INMay 20-22, 2004

  2. Team Members Design F. J. Barbosa Ed Jastrzembski James Proffitt Layout Jeff Wilson Production Chris Cuevas Software David Abbott QC & Rework Bill Gunning Signal Hub Mark Taylor

  3. A Brief History Discussions on a high resolution TDC for use in Hall D started in late 1999. Other JLAB users showed interest in a high resolution TDC - design work started in mid 2000. Two fully functional prototypes tested in 2002. Results were presented at the 2002 IEEE NSS-MIC. Production of 50 units has been completed for Hall C and other users at JLAB in early 2004.

  4. F1TDC Specifications Packaging 6U VME64x Inputs Differential ECL (110 Ohm) 64 Channels @ 120 pS LSB 32 Channels @ 60 pS LSB Control START, SYNCRES, TRIGGER Front Panel – Differential ECL (110 Ohm) Backplane – Differential LVPECL (110 Ohm) Clock Differential LVPECL (110 Ohm) – 40 MHz Internal, Front Panel, Backplane Dynamic 7.8 uS (for 120 pS LSB) Range 3.9 uS (for 60 pS LSB) Standard Less than 0.9 LSB Deviation INL 0 LSB DNL 10-50% LSB Acquisition Trigger Matching w/ Zero suppression Programmable Trigger Window and Latency FIFO 1 M TDC Data Words Interface 32-bit VME Block Transfers (>20 Mbyte/s) 64-bit VME Block Transfers (>40 Mbyte/s) Power+12V @ 0.5A -12V @ 0.4A +3.3V @ 7.3A +5V @ 1.8A

  5. Project Status A few ECOs and rework performed after receipt of units. All 50 production units tested after a burn-in period of at least 72 hours: 34 Pass, 16 Need Further Checks 64-bit data readout available (40 Mbytes/s). Multi-block readout functioning properly (multiple boards – single logical read). Backplane signal distribution hub has been designed. Layout is close to completion. User’s Manual available online at www.jlab.org/exp_prog/electronics/manuals

  6. Project Status (cont.) Two software initiatives: Functional Testing – single board lab bench testing. For Users – library created to be used within VxWorks. Software library contains code to access, initialize, configure, control, and readout of a crate full of F1TDC boards (up to 20). Transparency – the user does not need intimate knowledge of the F1 chip control registers, timing and order of programming. Library designed to be functionally independent but intended for CODA users: # Setup F1TDC f1Clear(F1_SLOT); f1EnableData(F1_SLOT,0xff); /*all 8 chips*/ f1SetBlockLevel(F1_SLOT,1); /*read 1 event at a time*/ f1EnableBusError(F1_SLOT);

  7. Schedule Project on target to be completed by early July 2004.

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