1 / 19

Division

Division. Lecture L6.3. Division. 10. 1010. 13 135 13 05. 1101 10000111. 1101 00111 0000 01111 1101 00101 0000 0101. Division 8-bit/4-bit = 4:4. 1010. numer[8:0] denom[3:0]. _10000111 1101. 1101 10000111. 1101 00111 0000 01111 1101 00101 0000

coy
Download Presentation

Division

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Division Lecture L6.3

  2. Division 10 1010 13 135 13 05 1101 10000111 1101 00111 0000 01111 1101 00101 0000 0101

  3. Division 8-bit/4-bit = 4:4 1010 numer[8:0] denom[3:0] _10000111 1101 1101 10000111 1101 00111 0000 01111 1101 00101 0000 0101 If denom < numer[7:4] then overflow (quotient won’t fit in 4 bits) Let T = numer[8:4] N = numer[3:0] N2 = denom[3:0]

  4. Division 8-bit/4-bit = 4:4 T N 1010 shl 100001110 1101 1101 10000111 1101 00111 0000 01111 1101 00101 0000 0101 N2 for I in 0 to 3 loop shl T & N; if T[4:0] >= N2 then T := T - (0 & N2); N(0) := ‘1’; end if; end loop;

  5. sub1sll 001111110 1101 sll 011111100 1101 001011010 sub1sll rem quot Division 8-bit/4-bit = 4:4 T N 1010 sll 100001110 1101 1101 10000111 N2 1101 00111 0000 01111 1101 00101 0000 0101

  6. Combinational divide div.vhd -- Title: Division: 8/4 = 4:4 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity div is port ( numer: in STD_LOGIC_VECTOR (7 downto 0); denom: in STD_LOGIC_VECTOR (3 downto 0); quot: out STD_LOGIC_VECTOR (3 downto 0); remain: out STD_LOGIC_VECTOR (3 downto 0) ); end div;

  7. div.vhd (cont.) T N architecture div_arch of div is begin div1: process(numer, denom) variable T, N2: STD_LOGIC_VECTOR (4 downto 0); variable N: STD_LOGIC_VECTOR (3 downto 0); 100001110 1101 N2 begin T := '0' & numer(7 downto 4); N := numer(3 downto 0); N2 := '0' & denom;

  8. div.vhd (cont.) T N shl for I in 0 to 3 loop T := T(3 downto 0) & N(3); N := N(2 downto 0) & '0'; if T >= N2 then T := T - N2; N(0) := '1'; end if; end loop; quot <= N; remain <= T(3 downto 0); end process div1; end div_arch; 100001110 1101 N2

  9. div synthesized circuit denom(3:0) remain(3:0) quot(3:0) numer(7:0)

  10. Top-level Design x7seg IBUFG div

  11. DIVtest.vhd -- Title: DIV Test library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all; entity DIVtest is port( mclk : in STD_LOGIC; bn : in STD_LOGIC; SW : in STD_LOGIC_VECTOR(1 to 8); BTN : in STD_LOGIC_VECTOR(1 to 4); led: out std_logic; ldg : out STD_LOGIC; LD : out STD_LOGIC_VECTOR(1 to 8); AtoG : out STD_LOGIC_VECTOR(6 downto 0); A : out STD_LOGIC_VECTOR(3 downto 0) ); end DIVtest;

  12. architecture DIVtest_arch of DIVtest is signal r, p: std_logic_vector(15 downto 0); signal clr, clk, cclk, bnbuf: std_logic; signal clkdiv: std_logic_vector(26 downto 0); constant bus_width: positive := 4; begin U00: IBUFG port map (I => bn, O => bnbuf); led <= bnbuf; ldg <= '1'; -- enable 74HC373 latch clr <= bnbuf; -- Divide the master clock (50Mhz) process (mclk) begin if mclk = '1' and mclk'Event then clkdiv <= clkdiv + 1; end if; end process; -- clk <= mclk; -- 50 MHz WORKED --- clk <= clkdiv(0); -- 25 MHz WORKED -- clk <= clkdiv(1); -- 12.5 MHz -- clk <= clkdiv(24); -- 2 works -- clk <= bnbuf; cclk <= clkdiv(17); -- 190 Hz architecture DIVtest_arch of DIVtest is signal r, p: std_logic_vector(15 downto 0); signal clr, clk, cclk, bnbuf: std_logic; signal clkdiv: std_logic_vector(26 downto 0); constant bus_width: positive := 4; begin U00: IBUFG port map (I => bn, O => bnbuf); led <= bnbuf; ldg <= '1'; -- enable 74HC373 latch clr <= bnbuf; -- Divide the master clock (50Mhz) process (mclk) begin if mclk = '1' and mclk'Event then clkdiv <= clkdiv + 1; end if; endprocess; cclk <= clkdiv(17); -- 190 Hz

  13. p(15 downto 12) <= "0000"; p(7 downto 4) <= "0000"; U1: div port map (numer => SW, denom =>BTN(1 to 4), quot => p(3 downto 0), remain =>p(11 downto 8)); U3: x7seg port map (x => p, cclk => cclk, clr => clr, AtoG => AtoG, A => A); LD <= SW; end DIVtest_arch;

  14. A(3:0) x7seg AtoG(6:0)

  15. divg.vhd -- Title: Division: 2*width/width = width:width library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity divg is generic(width:positive); port ( numer: in STD_LOGIC_VECTOR (width+width-1 downto 0); denom: in STD_LOGIC_VECTOR (width-1 downto 0); quot: out STD_LOGIC_VECTOR (width-1 downto 0); remain: out STD_LOGIC_VECTOR (width-1 downto 0) ); end divg;

  16. divg.vhd (cont.) architecture divg_arch of divg is begin div1: process(numer, denom) variable T, N2: STD_LOGIC_VECTOR (width downto 0); variable N: STD_LOGIC_VECTOR (width-1 downto 0); begin T := '0' & numer(width+width-1 downto width); N2 := '0' & denom; N := numer(width-1 downto 0);

  17. begin T := '0' & numer(width+width-1 downto width); N2 := '0' & denom; N := numer(width-1 downto 0); for j in 0 to width-1 loop T := T(width-1 downto 0) & N(width-1); N := N(width-2 downto 0) & '0'; if T >= N2 then T := T - N2; N(0) := '1'; end if; end loop; quot <= N; remain <= T(width-1 downto 0); end process div1; end divg_arch;

  18. width = 8

  19. divg width = 8

More Related