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2011 ATLAS Upgrade Project

2011 ATLAS Upgrade Project. Purpose. Assemble a data acquisition teststand We have the hardware: HSIO (with an FPGA chip) and interface Single-Chip board is a place holder for a stave of the next generation of silicon detectors. Goal. HSIO+Interface. Interface ->. HSIO ->. Single-Chip.

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2011 ATLAS Upgrade Project

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  1. 2011 ATLAS Upgrade Project

  2. Purpose • Assemble a data acquisition teststand • We have the hardware: HSIO (with an FPGA chip) and interface • Single-Chip board is a place holder for a stave of the next generation of silicon detectors

  3. Goal

  4. HSIO+Interface Interface -> HSIO ->

  5. Single-Chip chip

  6. What we had to do to make things work • Upgrade computer (WASSUP) • Partition D: drive • Download C++, Xilinx, SCTDAQ, WinPCAP, Wireshark , Root software • Program FPGA with Xilinx • Make power/connection cables • Design stand for the board

  7. Software • Xilinx: FPGA programming • Wireshark: Shows whether or not board is talking to the computer • WinPCAP:capture packets travelling over a network • SCTDAQ: the software we’ll be using to run tests through root

  8. Configuring the software • Had to get BNL’s SCTDAQ software/config files • Rewrote all the paths in a .rootrc file to match our own: • Move some code around:

  9. Code moving cont. Adding the hex number of our ethernet adapter

  10. Running SCTDAQ • After fixing all of the config files, we were able to run SCTDAQ • It gets errors when the HSIO isn’t connected to the ABCn Single-Chip board, but the program is working at least

  11. Root output for SCTDAQ

  12. Making Cables • Needed power cables for the HSIO and Single-Chip boards • Needed a ribbon cable to connect the interface board to the Single-Chip

  13. HSIO Power • Four-pin molex connection • Provides 48v to the board which is converted down to 12v (the fan keeps the converter cool) Step 2: Connect and Profit Step 1: Solder Pins

  14. HSIO – Single Chip Interface • The ribbon cable needed to be altered. • Wires had to cross over to make the correct connections

  15. Single-Chip Power and Ribbon Cables The power cable wraps around the ribbon cable here

  16. Last-Minute Breakthrough Slide • Power-cycling the HSIO board after re-programming the FPGA fixed our communication problems • Boards acknowledge each other • Able to run tests with Single-Chip (although still wonky) • Looking into reproducing results from Freiburg/BNL

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