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# ç¬¬åå®å æ¯è¼å¨ ( æç§æ¸ç¬¬åç«  ) - PowerPoint PPT Presentation

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### 第四單元 比較器(教科書第十章)

http://140.127.194.152

Outline
• XOR閘和XNOR閘
• 4-bit比較器
• 同位產生器/檢知器
XOR閘 (p.311)
• 二輸入XOR
• 兩級三輸入XOR

X<= A xor B;

X<= A xor B xor C;

XNOR閘(p.312)
• 二輸入XNOR

4-bit比較器(p.314)
• 輸入A(A3A2A1A0),B(B3B2B1B0)，當A=B,Y=1否則Y=0。
• Y= (A3☉B3)(A2☉B2)(A1☉B1)(A0☉B0)  Demorgan’s law = (A3♁B3+ A2♁B2+A1♁B1+A0♁B0)’
4-bit比較器(p.314)
• IC 7485和4585，輸入A(A3A2A1A0)、B(B3B2B1B0)，串級輸入(Cascading input) ，輸出OUT(A>B, A=B, A<B)
• 串級輸入(後級)接前級輸出
4-bit比較器(p.314)

OUTS

A , B

CAS

A>B

A<B

A=B

OUTS<= “001" when A>B else

“100" when A<B else

CAS when A=B;

4-bit比較器(p.314)
• 單級(4-bit)
• 串級(8-bit)

• 同位(parity):將一個bit加入二進位碼，使產生偶數個”1”或奇數個”1”

• 四位元偶同位產生器真值表和電路圖
• Y= A’B’C’D+A’B’CD’+A’BC’D’+A’BCD+AB’C’D’+AB’CD+ABC’D+ABCD’ = A♁B♁C♁D  try to proof

E

A,B,C,D,E最後輸出偶數個“1”

• 同位應用在通訊系統

• 同位產生器和檢知器的電路圖，檢知器比產生器多一個xor閘

• 相同功能，兩種不同架構的電路，圖A為完全串級，圖B為並級和串級混合
• 圖B的優點:減少串級延遲

Y=[(A♁B)♁(C♁D)]♁[(E♁F)♁(G♁H)]