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Computer Systems and Device Management. Fred Kuhns. Operating System. File Manager. Process & Resource Manager. Memory Manager. Device Manager. Processor(s). Main Memory. Devices. Hardware. OS Organization. OS Techniques.

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os organization

Operating System

File

Manager

Process & Resource

Manager

Memory

Manager

Device

Manager

Processor(s)

Main Memory

Devices

Hardware

OS Organization

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os techniques
OS Techniques
  • Controlling access to hardware resources is done using hardware supported privilege levels, typically two: user and system
  • Privileged operations, resource management, protection enforcement (isolation), and sharing performed by a trusted control program: the Kernel
  • Users request OS services using a well defined interface that validates user and notifies OS of request: two common methods:
    • System calls: trap changes mode and executes privileged code in context of calling process
    • Message passing: interface constructs message and sends to another system (i.e. privileged) process

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system call traditional monolithic kernel

char

block

Device drivers

System Call – Traditional Monolithic Kernel

execution environment

application

trap

libraries

user

System call interface

kernel

System Services

File subsystem

dispatcher

IPC

Process

control

subsystem

Buffercache

Scheduler

Exceptions

Interrupt

Memory

hardware

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message passing micro kernel

DB server

Memory mngr

Task mngr

I/O mngr

Message Passing – Micro-Kernel

Client

microkernel

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von neumann architecture

Arithmetic-Logical Unit

(ALU)

Control Unit

Primary Memory

Device Controller

Device

Device Controller

Device

Device Controller

Device

Device Controller

Device

Von Neumann Architecture

Central Processing Unit (CPU)

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slide7

An Example: Port Processors for an IP Router

ControlProcessor

Switch Fabric

ATM Switch Core

IPP

OPP

IPP

OPP

IPP

OPP

IPP

OPP

IPP

OPP

IPP

OPP

FPX

FPX

FPX

FPX

FPX

FPX

Port

Processors

SPC

SPC

SPC

SPC

SPC

SPC

LC

LC

LC

LC

LC

LC

Line Cards (link interfaces)

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slide8

Dist. Q. Ctl.

Dist. Q. Ctl.

Dist. Q. Ctl.

Dist. Q. Ctl.

FlowLookup

FlowLookup

Flow/RouteLookup

Flow/RouteLookup

Functional Diagram of the Port Processor (SPC)_

ControlProcessor

Switch Fabric

SPC

SPC

OutputPortProc.

InputPortProc.

. . .

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slide9

The Smart Port Card: an embedded processor

Switch Interface

DRAM

Link Interface

CPU Module

APIC

PCI Bus

System FPGA

Serial Ports

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slide10

Typical Pentium PC Architecture

Addr/Data

Ctrl

Ctrl

Cache

CPU

North-

Bridge

DRAM

Addr/Data/Ctrl

PCI Bus

Intr

NMI

INIT

SouthBridge (PIIX3)

(PIC, PIT, …)

PCI

Devices

ISA Bus

ISA

Devices

Super-IO

BIOS

BIOS

RTC

Uarts

Kbd/Mse

Floppy

Parallel

...

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zooming in on computer architecture

.

.

.

.

.

.

.

.

.

Zooming in on Computer Architecture

CPU

Memory

0

1

PC

MAR

IR

Reg N

Instruction

MBR

Reg 1

Reg 0

Instruction

I/O AR

Instruction

execution

unit

I/O BR

Data

Devices

Data

Data

Data

.

.

Buffers

N

PC - Program Counter

IR - Instruction Register

MAR - Memory Address Register

MBR - Memory Buffer Register

I/O AR - Input/Output Address Register

I/O BE - Input/Output Buffer Register

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processor registers
Processor Registers
  • User-visible registers
    • Enable programmer to minimize main-memory references by optimizing register use
  • Control and status registers
    • Used by processor to control operation of the processor
    • Used by operating-system routines to control the execution of programs

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user visible registers
User-Visible Registers
  • May be referenced by machine language
  • Available to all programs - application programs and system programs
  • Types of registers
    • Data - can be assigned by the programmer
    • Address - contain main memory address of data and instructions. Or may contain a portion of an address that is used to calculate the complete address.
    • Condition Code or flags

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control and status registers
Control and Status Registers
  • Program Counter (PC)
    • Contains the address of an instruction to be fetched
  • Instruction Register (IR)
    • Contains the instruction most recently fetched
  • Program Status Word (PSW)
    • condition codes
    • Interrupt enable/disable
    • Supervisor/user mode

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instruction cycle

Fetch Cycle

Execute Cycle

Fetch Next

Instruction

Execute

Instruction

HALT

START

Instruction Cycle
  • Processor fetches instruction from memory
  • PC contains address of next instruction to be fetched
  • PC incremented after each fetch

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modern instruction cycle
Modern Instruction Cycle
  • (a) A three-stage pipeline
  • (b) A superscalar CPU

(Stallings, Operating Systems, 4th Edition)

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example of program execution

CPU Registers

Memory

Memory

Memory

Memory

Memory

Memory

PC

300

AC

IR

1940

300

300

300

300

300

300

1 9 4 0

1 9 4 0

1 9 4 0

1 9 4 0

1 9 4 0

1 9 4 0

301

301

301

301

301

301

5 9 4 1

5 9 4 1

5 9 4 1

5 9 4 1

5 9 4 1

5 9 4 1

302

302

302

302

302

302

2 9 4 1

2 9 4 1

2 9 4 1

2 9 4 1

2 9 4 1

2 9 4 1

0 0 0 3

0 0 0 3

0 0 0 3

0 0 0 3

0 0 0 3

0 0 0 3

940

940

940

940

940

940

941

941

941

941

941

941

0 0 0 2

0 0 0 2

0 0 0 2

0 0 0 2

0 0 0 2

0 0 0 5

Example of Program Execution

CPU Registers

PC

301

AC

0003

IR

1940

1 - load

Step 1

Step 2

CPU Registers

CPU Registers

PC

301

PC

302

AC

0003

AC

0005

IR

5941

IR

5941

3 + 2 = 5

Step 3

Step 4

5 - add

CPU Registers

CPU Registers

PC

302

PC

303

AC

0005

AC

0005

IR

2941

IR

2941

2 - store

Step 5

Step 6

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interrupts devices notify cpu of some event

clock handler

Interrupts – devices notify CPU of some event

Processor

Device table

dispatcher

(interrupt handler)

X

Bus

command

status

rt-counter

Timer

Interrupt is generated every 10ms, used by OS for accounting and resource (CPU)

sharing.

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instruction cycle with interrupts
Instruction Cycle with Interrupts

Interrupt Cycle

Execute Cycle

Fetch Cycle

Interrupts Disabled

Check for &

Process Int

Fetch Next

Instruction

Execute

Instruction

START

Interrupts Enabled

HALT

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interrupt cycle
Interrupt Cycle
  • Processor checks for interrupts
  • If no interrupts fetch the next instruction for the current program
  • If an interrupt is pending
    • save current PC value
    • set PC to start of dispatcher
  • System interrupt dispatcher saves some general purpose registers, determines interrupt type (or id) and calls handler by indexing into an array of function pointers.

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simple interrupt processing
Simple Interrupt Processing

Hardware

Software

Device controller or

other system hardware

issues an interrupt

Save remainder of

process state

information

Processor finishes

execution of current

instruction

Processor signals

acknowledgment

of interrupt

Process interrupt

Processor pushes PSW

and PC onto control

stack

Restore process state

information

Processor loads new

PC value based on

interrupt

Restore old PSW

and PC

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what about multiple interrupts
What about Multiple Interrupts
  • Simple Approach - disable interrupts
  • Use Priorities to differentiate between interrupt classes
  • Disable interrupts so processor can complete task
  • Interrupts remain pending until the processor enables interrupts
  • After interrupt handler routine completes, the processor checks for additional interrupts

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i o and devices

Device Driver

I/O and Devices

Processor

Device table

dispatcher

(interrupt handler)

X

Bus

command

status

data 0

data 1

Device Controller

(firmware and logic)

...

data N-1

Device X

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i o techniques
I/O Techniques
  • Direct I/O with polling, aka Programmed I/O
    • Processor does all the work. Poll for results.
  • Interrupt Driven I/O
    • Device notifies CPU when I/O operation complete
  • Memory Mapped I/O
    • rather than reading/writing to controller registers the device is mapped into the OS memory space
    • increased efficiency
  • Direct memory access (DMA)
    • DMA controller read and write directly to memory, freeing the CPU to do other things.
    • CPU notified when DMA complete

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programmed i o

Insert Read

command to

I/O Module

CPU I/O

Read Status

of I/O

Module

I/O CPU

Not

Ready

Error

Condition

Check

Status

Ready

Read word

from I/O

Module

I/O CPU

Write word

into memory

CPU Memory

No

Done?

Yes

Next Instruction

Programmed I/O
  • Processor transfer data to/from device.
  • Read/write directly to status and command registers
  • Processor polls device for status
  • Consumes a lot of processor time because every word read or written passes through the processor

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interrupt driven i o

Insert Read

command to

I/O Module

CPU I/O

Do something

else

Read Status

of I/O

Module

Interrupt

I/O CPU

Error

Condition

Check

Status

Ready

Read word

from I/O

Module

I/O CPU

Write word

into memory

CPU Memory

No

Done?

Yes

Next Instruction

Interrupt-Driven I/O
  • Similar to direct I/O but processor not required to poll device.
  • Interrupt asserted to notify processor of a change in status

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direct memory access dma

Issue Read

block command

to I/O module

CPU DMA

Do something

else

Read status

of DMA

module

Interrupt

DMA CPU

Next Instruction

Direct Memory Access (DMA)
  • I/O exchanges occur directly with memory
    • Processor grants I/O module authority to read from or write to memory
    • Relieves the processor from the task
    • Processor is free to do other things
  • An interrupt is sent when the task is complete
  • The processor is only involved at the beginning and end of the transfer

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another look at i o
Another Look at I/O
  • Synchronous (Programmed I/O) - control returns to user program only upon I/O completion.
    • Idle CPU until the next interrupt
    • wait loop (contention for memory access).
  • Asynchronous (Interrupt driven I/O) - control returns to user program before I/O completion.
    • System call – request to the operating system to allow user to wait for I/O completion.
    • Device-status table contains entry for each I/O device indicating its type, address, and state.

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synchronous versus asynchronous
Synchronous Versus Asynchronous

Synchronous

Asynchronous

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