Full Tree Multipliers

1. Full Tree Multipliers • All k PPs Produced Simultaneously • Input to k-input Multioperand Tree • Multiples of a (Binary, High-Radix or Recoded) Formed at Top of Tree • Multiple-Forming Circuits • AND Gates (binary multiplier) • radix-4 Booth (recoded multiplier) • Tree Results in Product in Redundant Form(2 Values – Carry-Store for Example) • Final Product Formed With Converter(Fast CPA for Exmaple)

2. General Parallel Multiplier

3. Tree Type Multiplier Classification • Distinguished by Design of: • Partial Product Forming Circuits (i.e. Booth, Hi-Rad, etc.) • Reduction Tree Type • Redundant-to-Binary Converter • If Redundant Result in Carry-Save Form, Converter is Just a CPA • Could Use Other Redundant Adders Such as Signed Binary (4:2 Compressors) • High Radix Multipliers Lead to Fewer Values to Accumulate • Sequential Design – Fewer Cycles • Parallel Design Smaller Tree • Tradeoff Tree Complexity Versus Multiple Forming Circuit

4. Wallace and Dadda Tree Multipliers • Wallace – Combine Partial Products as Soon as Possible • Dadda – Maintain Critical Path Length (Tree Depth) but Combine as Late as Possible • Wallace – Fastest Possible Design Since Typically Smaller CPA at End • Dadda – Simpler Tree but Wider CPA at End

5. 4  4 Example • 16 AND Gates Used to Form xiaj Terms (dots)  1 2 3 4 3 2 1

6. Wallace Example 1 2 3 4 3 2 1 • 5 FAs, 3 HAs, 4-bit CPA

7. Dadda Example 1 2 3 4 3 2 1 • 4 FAs, 2 HAs, 6-bit CPA

8. Trees in Numeric Representation • Many Times Hybrid Approach Used to Find Smallest Width CPA • MS Thesis Topic – Optimize Tree With Different Counter Types

9. Implementation Issues • Logarithmic Depth Tree – Irregular Structure • Design/Layout Difficult • Various Length Signal Propagation Paths • Hazards and Signal Skew • Need Iterated Recursive Structures • Automatic Synthesis and Layout • Motivates Search for Alternative Reduction Tree Structures

10. Other Tree Architectures • Can Compose from Larger Counters, e.g. (7:2) • Use “0” Inputs for Some • Or Prune the Tree for Some • Use “slices” – Example is (11:2) – Next Slide • Can be Laid Out to Occupy Narrow Vertical Slice and Replicated • All Carries Produced in Level i Enter Level i+1 • Balanced Delay Tree Results • 3 Columns – 1, 3, 5 FAs • Can Expand from 11 to 18 – Append Col. of 7

11. (11:2) Tree Slice

12. Other Tree Blocks • Converter Stage is Fast CPA • Can Also Use SBD • With SBD the Converter Stage is a Fast Subtractor

13. Array Multipliers • Can Eliminate Top CSA With 0 Input • Can Replace 0 With y to Compute ax+y

14. Array Multipliers • Tree is One-Sided • Longest Delay is 4 CSA Plus k-bit CPA • Slower than Wallace/Dadda Tree • Regular Structure • short wires in horiz., vert., diag. positions • simple, efficient layout • easily pipelined (latches after each CSA row)

15. Methods for Reducing Array Size

16. Reducing Array Size (cont.)

17. 5 by 5 Array Multiplier (unsgnd)

18. Signed Array Multiplier • Array with 2’s Complement • Alternative is Pezaris Array with Different Cell Types • Need Array of AND Gates for Multiple Generation • Critical Path is Main Diagonal then Ripple Thru CPA • Can skip “h” Cells Along Main Diag • lower right cell now has 4 inputs • move to “extra” input in second cell in diag. • less regular layout now but faster

19. 5 by 5 Array Multiplier (signd)

20. 5 by 5 Array Multiplier • AND Gates Embedded inside FA Blocks

21. Pipelined Partial Tree Multiplier

22. Pipelined Array Multiplier