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Computer Architecture From Many Perspectives

Computer Architecture From Many Perspectives. Peter Hsu, Ph.D. Presented 13 September 2001 at Department d’Arquitectura de Computadors, Universitat Polit è cnica de Catalunya (UPC), Barcelona, Spain. Industry’s View. Computer architecture vs. design ?

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Computer Architecture From Many Perspectives

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  1. Computer Architecture From Many Perspectives Peter Hsu, Ph.D. Presented 13 September 2001 at Department d’Arquitectura de Computadors, Universitat Politècnica de Catalunya (UPC), Barcelona, Spain

  2. Industry’s View • Computer architecture vs. design? • Tradition: Architect creates a plan to transform client’s desire into physical reality • Interpretation: • Plan = logical design, project schedule, cost projections, … • Reality = mechanical, thermal, electrical issues; reliability, … • Desire = profit, return on investment

  3. Agenda • Challenge to think more broadly about computer design • Physics: materials, signal integrity, … • Manufacturing: tolerances, infrastructure, … • Financial: design, fabrication costs, … • Interconnected-ness of issues, solutions • Architect interface many different audiences • Optimality depends of scope of view • Novel solutions to current problems

  4. Presentation Methodology • By examples • Office environment multiprocessor server • Mechanical, manufacturing issues • Electrical signal, supply issues • 3-D graphics chip for PC • Project scheduling, costs, return on investment

  5. Caveats Author’s bias: performance •  latency (memory, inter-processor, etc.), •  bandwidth, then •  micro-architecture Decisions for presentation clarity • Not advocating particular design • No claims of “right” formula, ways of doing things • One person’s opinion; “your mileage may vary”

  6. Example #1 Office environment multiprocessor server • Topics: • Interconnect/packaging scheme • Manufacturability considerations  performance • Material characteristics  micro-architecture • Power supply • Product usage environment  micro-architecture

  7. Interconnect/Packaging • Assumptions • Multiple chips (more powerful than desktop) • Not cheap (e.g. US$50,000) • Have control of CPU design • i.e. Traditional computer system company • Approach: • Low latency  physically close together

  8. heat distributor 88 chip stacks 10mm alignment cage silicon substrate 14cm 12mm 4mm printed circuit board  3000 wire bonds pressure plate Multichip Module

  9. 10m width 20m pitch 12mm Chip Stack 12mm 0.3mm router 10mm DRAMs processors stack shown upside down

  10. Manufacturing Issues • Stacking technology • Limited production today, not discussed here • Silicon substrate • Process compatibility, availability • Mechanically compliant connection • Thermal expansion mismatch, reliability • Repair strategy • Inventory, product mix

  11. Silicon Substrate 4mm 12mm maximum trace length 24.8cm 12mm chip maximum cut-set 2048 p-to-p links 4mm spacer 200mm (8 inch) wafer 150m pitch 3200 wire bonds substrate to PCB 14cm

  12. Stack to Substrate Connection wirebond springs heat conventional wirebond pads DRAMs router chip silicon substrate

  13. alignment cage 75m tolerance substrate chip stack 250m pitch 75m clearance (0.003 inch or 3 mils) 125m pad 125m space chip stack Mechanical Constraints • Machined parts need several mils tolerance

  14. Implications • Manufacturing infrastructure • 64 stacks, 200mm wafer  12×12mm die • 250µm pad pitch  2304 pads • Thermal density • Stacked CPU’s not feasible Goal: low latency interconnect scheme in this context

  15. 6464 Full Crossbar? • Tradeoffs  Electrical delay: off-chip crossings, data skew  Logical latency: contention, queuing  Per-link bandwidth: memory hot-spots • Design • Source Synchronous Links • 8 data, 2 (differential) clock wires (20% overhead) • 63210  1260 signals / stack (45% power/ground) • Cut-set: 20,480 signals (track  7m)

  16. Physics • Delay distance (speed of light) • Distant bandwidth  wire pipelining  transmission line low resistance • R< Z0 reflections, need terminator • Z0 ≤ R≤ 2Z0 self terminating • 2Z0 < Rcannot wave pipeline • Impedance Z0 is function of material, dimensions

  17. ( ) ( ) 0.222 0.222 ( ) ( ) ( ) 0.222 W T H T C  W T H T H T = 1.15 + 2.80 [ ] + 0.06 + 1.66  0.14 L W  H   C0 C ( ) 1.34 R =  Z0 = T S Basic Formulas Bakoglu, H.B., Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, 1990

  18. Design Challenge • Materials • Copper,   1.7 mcm • “Low-K” Insulator,   3.0 • Problem • Cut-set narrow (4µm) wire • Corner-to-corner 25mm • Resistance ≈ 150Ω • ImpedanceZ0 ≈ 25Ω

  19. Interconnect Dimensions width W space S pitch 4 3.5 7.5 height H 6 VDD insulation thickness T 8 VSS 2 3 4.5 5 10 5.5 15 7.5

  20. Substrate • Features • Self-terminating transmission lines • 1 L  7.2cm R  51 Z0 27 • 2 L  18.4cm R  52 Z0 26 • 3 L  24.8cm R  47 Z0 27 • Integral power grid: shielding, image current • “Sweet spot” • Fast: sub- 2ns corner-to-corner • High bandwidth: 2 Gbits/s/wire • Cheap: 7 metal (3 X•Y  pad) wafer, 2µm lithography

  21. Power Considerations • Installation environment • Home, office, server room? • Heat Density • Liquid cooling, heat pipe? • Heat Dissipation • Physical size, fan noise?

  22. 10% variation 15A 110V AC -5% first stage 120A 12V DC -10% 1,280A 1V DC second stage Energy • Office (USA) • Peak ≈1300W • Sustained ≈500W • Human comfort • Implications • Stack  20W

  23. router 3W logic + 1W substrate (4W total) 41W active simultaneously (4W total) DRAMs 10W CPU + 2W L2 cache (12W total) Processor Implications • Limit • MHz • CPU micro-architecture • Memory bandwidth • Router performance • …

  24. Example #2 3-D graphics chip for PC • Topics • Design cost • Example numbers (huge variances!) • Return on investment • Impact on development cost

  25. 2nd tapeout Years Architecture Logical Design (RTL) Logical Verification Physical Design (Synthesis, P&R) Physical Verification (Timing) Prototype Fabrication, Package Silicon Debug In-System Verification 2nd Physical Design 2nd Physical Verification Production Fabrication 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 9 months 1st tapeout 9 months 12 month 9 month customer samples 6 month 3 2 4 6 month 3 Variations Startup company: architecture –6 Big company: verification +6 3 Example Project Schedule

  26. Years Performance Logical Design Logical Verification Physical Design Physical Verification Package Design Reference Board Design In-System Verification 2nd Physical Design 2nd Physical Verification Documentation 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 2 – 10 5 – 25 People 5 – 25 5 - 50 2 - 30 1 - 3 1 - 5 Range: Startup – mature company 1 - 5 Example Resource Needs

  27. Costs • Development • Approximation: person year = $ ⅓ M • $150K Salary + 50% Benefits + 50% Equipment + 20% Facilities • Variation ($20M - $200M) risk exposure • Fallacy: design cost design complexity • Manufacturing • 60mm2 die ≈ $10 (estimate 70% yield) • Ball grid array package, assembly ≈ $5

  28. Return On Investment • Factors • Amount of money expended • Time value • Opportunity cost • Reasonable ROI: 5-10 after 4 years • New development very risky compared to selling existing products • Many, many non-technical risks

  29. Case Study • PC graphics chip • $20M development, 3 years • $15 per-unit manufacturing cost • Lifetime volume: 2M units? • Desired price: $15 + 5($20M/2M units) = $65 Architecture impacts development cost: e.g. super-pipeline  circuit style  CAD tools  people resources

  30. Conclusion • Industrial computer architecture: plan mapping vision to reality • Vision • Performance goals; micro-architecture, ROI, … • Reality • Electrical, mechanical, thermal physics; financial constraints; people’s feelings; … • Plan • “Convince me to bet on you…” [author’s opinion]

  31. Comment • As computer industry moves to “System-On-a-Chip” (SOC) products, there is a huge demand for computer architects that understand and are able to optimize in broad contexts.

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