An Announcement

1. An Announcement Our lab class will start on the next week. Please see your schedule. Our section list name will divide into 35 students. First 35 will be in first class on the section and the reminder will be in the next class for that section.

2. Firkhan Ali Bin Hamid AliComputer ArchitectureBIC 10503 Chapter 02: System Buses

3. Program Concept Hardwired systems are inflexible General purpose hardware can do different tasks, given correct control signals Instead of re-wiring, supply a new set of control signals

4. What is a program? A sequence of steps For each step, an arithmetic or logical operation is done For each operation, a different set of control signals is needed

5. Function of Control Unit • For each operation a unique code is provided • e.g. ADD, MOVE • A hardware segment accepts the code and issues the control signals • We have a computer!

6. Components • The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit • Data and instructions need to get into the system and results out • Input/output • Temporary storage of code and results is needed • Main memory

7. Computer Components:Top Level View

8. Instruction Cycle • Two steps: • Fetch • Execute

9. Fetch Cycle • Program Counter (PC) holds address of next instruction to fetch • Processor fetches instruction from memory location pointed to by PC • Increment PC • Unless told otherwise • Instruction loaded into Instruction Register (IR) • Processor interprets instruction and performs required actions

10. Execute Cycle • Processor-memory • data transfer between CPU and main memory • Processor I/O • Data transfer between CPU and I/O module • Data processing • Some arithmetic or logical operation on data • Control • Alteration of sequence of operations • e.g. jump • Combination of above

11. Example of Program Execution

12. Example of Program Execution • Step 1; • PC contain 300 (address of 1st instruction) • This instruction is loaded into IR • This process would involve the use of a MAR + MBR • Step 2; • 1st 4 bits in IR indicate that the AC is to be loaded • The remaining 12 bits specify the address  940 • Step 3; • PC incremented & next instruction is fetch

13. Example of Program Execution • Step 4; • The old contents of the AC & the contents of location 941 are added & result is stored in AC • Step 5; • PC is incremented & the next instruction is fetched • Step 6; • Content of the AC are stored in location 941

14. Instruction Cycle State Diagram

15. Instruction Cycle State Diagram • Instruction Address Calculation; • Determine the next address of the next instruction to be executed • Instruction Fetch; • Read instruction from its memory location into the processor • Instruction Operation Decoding; • Analyze instruction to determine type of operation to be perform & operands to be used

16. Instruction Cycle State Diagram • Operand Address Calculation; • If the operand involves reference to an operand in memory/available via I/O, then determine the address of the operand • Operand Fetch; • Fetch operand from memory or read it in from I/O • Data Operand; • Perform the operation indicated in the instruction • Operand Store; • Write the result into memory or out to I/O

17. Interrupts • Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing • Program • e.g. overflow, division by zero • Timer • Generated by internal processor timer • Used in pre-emptive multi-tasking • I/O • from I/O controller • Hardware failure • e.g. memory parity error

18. Program Flow Control

19. Interrupt Cycle • Added to instruction cycle • Processor checks for interrupt • Indicated by an interrupt signal • If no interrupt, fetch next instruction • If interrupt pending: • Suspend execution of current program • Save context • Set PC to start address of interrupt handler routine • Process interrupt • Restore context and continue interrupted program

20. Transfer of Control via Interrupts

21. Instruction Cycle with Interrupts

22. Program TimingShort I/O Wait

23. Program TimingLong I/O Wait

24. Instruction Cycle (with Interrupts) - State Diagram

25. Multiple Interrupts • Disable interrupts • Processor will ignore further interrupts whilst processing one interrupt • Interrupts remain pending and are checked after first interrupt has been processed • Interrupts handled in sequence as they occur • Define priorities • Low priority interrupts can be interrupted by higher priority interrupts • When higher priority interrupt has been processed, processor returns to previous interrupt

26. Multiple Interrupts - Sequential

27. Multiple Interrupts – Nested

28. Time Sequence of Multiple Interrupts

29. Connecting • All the units must be connected • Different type of connection for different type of unit • Memory • Input/Output • CPU

30. Computer Modules

31. Memory Connection • Receives and sends data • Receives addresses (of locations) • Receives control signals • Read • Write • Timing

32. Input/Output Connection(1) • Similar to memory from computer’s viewpoint • Output • Receive data from computer • Send data to peripheral • Input • Receive data from peripheral • Send data to computer

33. Input/Output Connection(2) • Receive control signals from computer • Send control signals to peripherals • e.g. spin disk • Receive addresses from computer • e.g. port number to identify peripheral • Send interrupt signals (control)

34. CPU Connection Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts

35. What is this?

36. Buses There are a number of possible interconnection systems Single and multiple BUS structures are most common e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP)

37. What is a Bus? • A communication pathway connecting 2 or more devices • Usually broadcast • Often grouped • A number of channels in one bus • e.g. 32 bit data bus is 32 separate single bit channels • Power lines may not be shown

38. Definition Bus a subsystem that transfers data or power between computer components inside a computer or between computers Typically controlled by device driver software. Bus is different from port Buses connect multiple devices Ports are only for two devices Processor Input Control Memory Datapath Output

39. Bus

40. Bus Hierarchy The Processor Bus (highest-level bus) Used to send information to and from the processor. The Cache Bus (higher-level) Also called backside bus – used to access the system cache The Memory Bus (second-level) Connects memory subsystem to the chipset and processor The Local I/O Bus Used for connecting performance-critical peripheral to the memory, chipset and processor, e.g. PCI The Standard I/O Bus Used for slower peripherals, e.g. mice, modems, low-speed networking For compatibility with older devices, e.g. ISA

42. Organization of Bus Control unit (CU) of the processor communicates with the rest of the architecture through a processor bus. Processor bus consists of three distinct sets of wires: address bus, data bus and control bus. Address bus used to communicate an address Data bus used to communicate data Control bus functions other than those of the address and data buses, especially signals that tell when the information on the address and data buses is valid.

43. Data Bus • Carries data • Remember that there is no difference between “data” and “instruction” at this level • Width is a key determinant of performance • 8, 16, 32, 64 bit

44. Data Bus carry information between the source and the destination Data and Addresses Complex commands

45. Address Bus • Identify the source or destination of data • e.g. CPU needs to read an instruction (data) from a given location in memory • Bus width determines maximum memory capacity of system • e.g. 8080 has 16 bit address bus giving 64k address space

46. Address Bus used by CPUs or DMA-capable (Direct Memory Access) units for communicating the physical addresses of computer memory elements/locations that the requesting unit wants to access (read/write). The width of an address bus determines how much memory can be accessed. The more address lines a CPU has, the more memory the CPU can address directly. e.g. a 16-bits address bus can reach 216=65,536 memory locations.

47. Control Bus Control how the processor communicates with the rest of the system. Signal requests and acknowledgments Indicate what type of information is on the data lines There are two lines on the control bus, read and write, which specify the direction of data flow. The CPU sends data to memory (write) and receives data from memory (read) on the data bus.

48. Control Bus • Control and timing information • Memory read/write signal • Interrupt request • Clock signals

49. Bus Speed The speed of the bus reflects how many bits of information can be sent across each wire each second. Most buses transmit one bit of data per line, per clock cycle. Although: Newer high-performance buses, e.g. AGP, may perform faster Older buses, e.g. ISA bus,perform slower.

50. Bus Bandwidth Bandwidthrefers to the total amount of data that can theoretically be transferred on the bus in a given unit of time. also called throughput reflects the amount of traffic that the channel can convey per second. Say it is “theoretical” because most bus cannot actually transmit data as maximum as stated in the calculated bandwidth • Bandwidth (MBytes/s) = width (Mbytes) * speed (Hz)