Design Implementation

1. ETEG 431 SG Design Implementation • ASIC: Application Specific Integrated Circuit • PLD: Programmable Logic Device • FPGA: Field Programmable Gate Array • _______________________________________ • >> Buzzwords and Acronyms Full Custom ICs, ASICs & PLDs

2. ETEG 431 SG Design Implementation • Logic Design • Circuit Design • Physical Design • Test Generation • Fabrication • Validation To Build a Chip Many Different Layers

3. ETEG 431 SG Design Implementation A CMOS Gate

4. ETEG 431 SG Design Implementation P Well (NMOS): As viewed from above

5. Full-Custom Standard Cells Compiled Cells Macro Cells Pre-diffused Pre-wired (Gate Arrays) (FPGAs) ETEG 431 SG Design Implementation Full-Custom Semi-Custom Cell-based Array-based Implementation Choices Standard Cells Pre-diffused Pre-wired Macro Cells Compiled Cells (Gate Arrays) (FPGAs) Full Custom ASIC PLD

6. ETEG 431 SG • Full Custom: Run all processes • Logical, Physical, Diffusion, Metal • Gate Array (Sea of Gates): Change Metal Layer • Logical, Simple Physical, Metal • Standard Cell: Change all Layers • Logical, Simple Physical, Diffusion, Metal • PLD (FPGA) : Program • Logical, Simple Physical Design Implementation Implementation Choices (Processes)

7. ETEG 431 SG • FPGA • Gate Array • Standard Cell • Full Custom Design Implementation Implementation Choices (Time to Market)

8. ETEG 431 SG • Development cost • (lowest to highest) • FPGA • Gate Array • Standard Cell • Full Custom Design Implementation • Device cost • (lowest to highest) • Full Custom • Standard Cell • Gate Array • FPGA Implementation Choices (Cost)

9. ETEG 431 SG Design Implementation Implementation Choices (Typical Volume Concept)

10. ETEG 431 SG Design Implementation Implementation Choices (Time Critical Market Volume)