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Design, Simulation and synthesis of ADSL ATU-C Transport Class 4 Transmitter

Design, Simulation and synthesis of ADSL ATU-C Transport Class 4 Transmitter. By Team 4 Winter Y2K for ELEN 603 at SCU. Objective. Study the IEEE ANSI T1.413 Standards. Formulate the specifications of the project. Create the VHDL Code. Simulate individual components Test Bench.

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Design, Simulation and synthesis of ADSL ATU-C Transport Class 4 Transmitter

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  1. Design, Simulation and synthesis ofADSL ATU-C Transport Class 4Transmitter By Team 4 Winter Y2K for ELEN 603 at SCU

  2. Objective • Study the IEEE ANSI T1.413 Standards. • Formulate the specifications of the project. • Create the VHDL Code. • Simulate individual components Test Bench. • Simulate, Analyze, synthesize and Report the overall system.

  3. AS0: Simplex Channel 1.536 MBPS DR = 48*8*4000 Ps Goes to Interleaved. LS0: C-Channel 16 KBPS DR = 1/2*8*4000 Goes to Interleaved. LS1: Duplex Channel 160KBPS DR=5*8*4000 PS Goes to Fast Data Buf. EOC (Embedded Operators Channel) not supported. Input Data Channels

  4. Frames • Interleaved Frame carries AS0 and LS0. • It requires Sync Byte, AEX and LEX bytes. • Fast Frame carries fast byte, 5 Bytes of LS1 and LEX Byte. • Super Frames contains 68 frames. • Last frame is the sync frame. • 0,1, 34 and 35 are filled with CRC and IBS.

  5. ADSL Transmitter components • Mux/Sync • SuperFramer • Scrambler • CRC • FEC (not completed) • Interleaver

  6. Mux/Sync • Multiplexed different Channels • Control flow of data through different modules • Synchronized clocks through the sub components

  7. Scrambler • Achieve d.c balance? (is that correct?) • Avoid long sequence of “0”s and “1”s. • Make the data more random • Use polynomials to scramble

  8. CRC (Cyclic redundancy codes) • Checks Validity of data and redundancy. • Use polynomials to add CRC bits. • Creates a CRC data for a superframe.

  9. FEC (not done) • Add redundancy Check Bytes according to message and check polynomials. • This was not done because of lack of time and resources.

  10. Interleaver • Spreads the bytes so that they experience independent errors. • Mix up various frames on the Interleave • The effect of the error is spread over the message so that it is possible to recover the data.

  11. Simulation Results • Individual Test Benches were created. • Check and Verification. • Integration piece by piece. • Results. • Unexpected surprises.

  12. Analysis & Conclusion • Used Exemplar Logic. • Not enough time to fully complete all components. • Inconsistencies and unexpected errors. • Able to Simulate and Verify the behavior of most components. • We learned a lot the very hard way.

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