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Device Characterization. ECE/ChE 4752: Microelectronics Processing Laboratory. Gary S. May April 1, 2004. Outline. NMOS Device Physics PMOS Device Physics CMOS Inverter. MOSFET. MOSFET = “Metal-Oxide-Semiconductor Field-Effect Transistor” Terminals: G = gate D = drain S = source

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device characterization

Device Characterization

ECE/ChE 4752: Microelectronics Processing Laboratory

Gary S. May

April 1, 2004

outline
Outline
  • NMOS Device Physics
  • PMOS Device Physics
  • CMOS Inverter
mosfet
MOSFET
  • MOSFET = “Metal-Oxide-Semiconductor Field-Effect Transistor”
  • Terminals:
    • G = gate
    • D = drain
    • S = source
    • B = body (substrate)
mosfet key quantities
MOSFET Key Quantities
  • Currents:
    • IG = 0 (due to insulating oxide layer)
    • ID
    • IS

=> since IG = 0, ID = IS (Kirchhoff’s Current Law)

  • Voltages:
    • VG
    • VD
    • VS = 0 (usually)
    • VB = 0 (usually)
  • Most important quantities: ID, VGS, VDS
biasing
1) Source and substrate grounded (zero voltage)

2) (+) voltage on the gate

Attracts e-s to Si/SiO2 interface

When threshold voltage (VGS = VTn) is reached, an inversion layer is formed

3) (+) voltage on the drain

e-s in the channel drift from source to drain

current flows from drain to source

Biasing
i v characteristics
I-V Characteristics
  • IDn vs. VGS:
  • VTn = “threshold voltage”
    • Voltage where Si/SiO2 interface becomes strongly inverted with electrons
    • Voltage were NMOS transistor “turns on”
linear region
Linear Region
  • Labeled “(1)” on previous plot
  • IDn = f(VGS, VDS) and VDS < VGS – VTn, VGS≥ VTn
  • Equation:

where: mn = electron mobility in the channel, Cox = eox/tox, tox = oxide thickness, eox = oxide permittivity (3.9e0 for SiO2)

saturation region
Saturation Region
  • Labeled “(2)” on the previous plot
  • IDnsat = f(VGS) and VDS≥ VGS – VTn, VGS≥ VTn
  • Equation:
transconductance
Transconductance
  • In the saturation region:

where: “Q” represents the quiescent operating point (i.e., fixed DC values of VGS, VDS)

outline1
Outline
  • NMOS Device Physics
  • PMOS Device Physics
  • CMOS Inverter
cross section
Cross-Section
  • Appropriate I-V equations found by:

1) reversing the direction of ID

2) reversing the polarity of all bias voltages (VBS => VSB, VGS => VSG, VDS => VSD)

biasing1
1) Source and substrate grounded (zero voltage)

2) (-) voltage on the gate

Attracts h+s to Si/SiO2 interface

When threshold voltage (VSG = -VTp) is reached, an inversion layer is formed

3) (-) voltage on the drain

h+s in the channel drift from source to drain

current flows from source to drain

Biasing
currents
Currents
  • Linear: VSD≤ VSG + VTp, VSG≥ -VTp
  • Saturation: VSD ≥ VSG + VTp, VSG ≥ -VTp
outline2
Outline
  • NMOS Device Physics
  • PMOS Device Physics
  • CMOS Inverter
inverter logic
Inverter Logic
  • Logic symbol:
  • Function:
  • Truth table:
ideal voltage transfer characteristic
Ideal Voltage Transfer Characteristic

V+ = supply voltage

VM = V+/2 = switching point of inverter (where input voltage = output voltage)

voltage definitions
Voltage Definitions
  • VIL = input voltage where slope of transfer characteristic is -1
  • VIH = larger input voltage where slope of transfer characteristic is -1
  • VOH = output voltage at input voltage of VIL
  • VOL = output voltage at input voltage of VIH
  • VM = voltage where output voltage equals input voltage
  • VMAX = output voltage when input voltage is zero (usually VMAX = V+)
  • VMIN = output voltage when input voltage is V+ (usually VMIN ~ 0)
voltage definitions cont
Voltage Definitions (cont.)
  • VOH = minimum output voltage for valid logic 1
  • VOL = maximum output voltage for valid logic 0
  • VIH = minimum input voltage for valid logic 0
  • VIL = maximum input voltage for valid logic 1
noise margins
Noise Margins
  • Noise = unwanted variations in voltage which, if too great, can cause logic errors
  • Noise margin high (NMH): tolerable voltage range for which we interpret the inverter output as a logic 1

NMH = VOH – VIH

  • Noise margin low (NML): tolerable voltage range for which we interpret the inverter output as a logic 0

NML = VIL - VOL

switching dynamics
Switching Dynamics
  • Input high: turn on bottom switch and discharge capacitive load
    • PMOS off
    • NMOS on (linear)
  • Input low: turn on the top switch and charge capacitive load
    • PMOS on (linear)
    • NMOS off
vtc another look
VTC: Another Look

(1) Input voltage = 0 V, output voltage = VDD

(2) NMOS saturated, PMOS linear

(3) Both transistors saturated

(4) NMOS linear, PMOS saturated

(5) Input voltage = VDD, output voltage = 0 V

approximate vtc
Approximate VTC

VOH = VMAX;VOL = VMIN

VM is input voltage where VOUT =VIN = VM

currents1
Currents
  • NMOS current at VIN = VM is:
  • PMOS current at VIN = VM is:
deriving v m
Deriving VM
  • Define:

and

  • Setting IDn = -IDp gives:
computing noise margins
Computing Noise Margins
  • To compute noise margins, the next step is to calculate VIL and VIH
  • Do so by determining the slope of the transfer characteristic at VIN = VM (i.e., voltage gain)
  • Then:
    • Project a line to intersect at VOUT = VMIN = 0 V to find VIH
    • Project a line to intersect at VOUT = VMAX = VDD to find VIL
voltage gain
Voltage Gain
  • Voltage gain can be shown to be:

where: ron and rop are output resistances of the NMOS and PMOS transistors, respectively

    • In general: and
    • We can find ro by inverting the slope of the ID vs. VDS characteristic
noise margins1
Noise Margins
  • We can find VIL and VIH using the slope (Av) of the VTC:
  • Noise margins:
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