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Sequential Logic Implementation. Models for representing sequential circuits Finite-state machines (Moore and Mealy) Representation of memory (states) Changes in state (transitions) Design procedure State diagrams State transition table Next state functions. OUT1. OUT2. OUT3. OUT4.

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Sequential Logic Implementation


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    1. Sequential Logic Implementation • Models for representing sequential circuits • Finite-state machines (Moore and Mealy) • Representation of memory (states) • Changes in state (transitions) • Design procedure • State diagrams • State transition table • Next state functions CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 1

    2. OUT1 OUT2 OUT3 OUT4 "0" R S R S R S R S D Q D Q D Q D Q CLK IN1 IN2 IN3 IN4 Registers • Collections of flip-flops with similar controls and logic • Stored values somehow related (e.g., form binary value) • Share clock, reset, and set lines • Similar logic at each stage • Examples • Shift registers • Counters CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 2

    3. OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q IN CLK Shift Register • Holds samples of input • Store last 4 input values in sequence • 4-bit shift register: CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 3

    4. Shift Register Verilog module shift_reg (out4, out3, out2, out1, in, clk); output out4, out3, out2, out1; input in, clk; reg out4, out3, out2, out1; always @(posedge clk) begin out4 <= out3; out3 <= out2; out2 <= out1; out1 <= in; end endmodule CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 4

    5. Shift Register Verilog module shift_reg (out, in, clk); output [4:1] out; input in, clk; reg [4:1] out; always @(posedge clk) begin out <= {out[3:1], in}; end endmodule CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 5

    6. output left_in right_out left_out right_in clear s0 clock s1 input Universal Shift Register • Holds 4 values • Serial or parallel inputs • Serial or parallel outputs • Permits shift left or right • Shift in new values from left or right clear sets the register contentsand output to 0s1 and s0 determine the shift function s0 s1 function 0 0 hold state 0 1 shift right 1 0 shift left 1 1 load new input CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 6

    7. 0 1 2 3 Design of Universal Shift Register • Consider one of the four flip-flops • New value at next clock cycle: Nth cell to N-1th cell to N+1th cell Q D CLK CLEAR clear s0 s1 new value 1 – – 0 0 0 0 output 0 0 1 output value of FF to left (shift right) 0 1 0 output value of FF to right (shift left) 0 1 1 input s0 and s1control mux Q[N-1](left) Q[N+1](right) Input[N] CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 7

    8. Universal Shift Register Verilog module univ_shift (out, lo, ro, in, li, ri, s, clr, clk); output [3:0] out; output lo, ro; input [3:0] in; input [1:0] s; input li, ri, clr, clk; reg [3:0] out; assign lo = out[3]; assign ro = out[0]; always @(posedge clk or clr) begin if (clr) out <= 0; else case (s) 3: out <= in; 2: out <= {out[2:0], ri}; 1: out <= {li, out[3:1]}; 0: out <= out; endcase end endmodule CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 8

    9. OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q IN CLK OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q IN CLK Counters • Sequences through a fixed set of patterns • In this case, 1000, 0100, 0010, 0001 • If one of the patterns is its initial state (by loading or set/reset) • Mobius (or Johnson) counter • In this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 11

    10. OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q CLK "1" Binary Counter • Logic between registers (not just multiplexer) • XOR decides when bit should be toggled • Always for low-order bit, only when first bit is true for second bit, and so on CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 12

    11. Binary Counter Verilog module shift_reg (out4, out3, out2, out1, clk); output out4, out3, out2, out1; input in, clk; reg out4, out3, out2, out1; always @(posedge clk) begin out4 <= (out1 & out2 & out3) ^ out4; out3 <= (out1 & out2) ^ out3; out2 <= out1 ^ out2; out1 <= out1 ^ 1b’1; end endmodule CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 13

    12. Binary Counter Verilog module shift_reg (out4, out3, out2, out1, clk); output [4:1] out; input in, clk; reg [4:1] out; always @(posedge clk) out <= out + 1; endmodule CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 14

    13. CombinationalLogic Inputs Outputs State Inputs State Outputs Storage Elements Abstraction of State Elements • Divide circuit into combinational logic and state • Localize feedback loops and make it easy to break cycles • Implementation of storage elements leads to various forms of sequential logic CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 17

    14. Clock Forms of Sequential Logic • Asynchronous sequential logic – state changes occur whenever state inputs change (elements may be simple wires or delay elements) • Synchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock) CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 18

    15. 010 111 001 In = 1 In = 0 In = 0 100 110 In = 1 Finite State Machine Representations • States: determined by possible values in sequential storage elements • Transitions: change of state • Clock: controls when state can change by controlling storage elements • Sequential Logic • Sequences through a series of states • Based on sequence of values on input signals • Clock period defines elements of sequence CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 19

    16. ERR closed not equal& new not equal& new not equal& new S3 S1 S2 OPEN closed mux=C1 closed mux=C2 closed mux=C3 reset open equal& new equal& new equal& new not new not new not new Example Finite State Machine Diagram • Combination lock from first lecture CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 20

    17. OUT1 OUT2 OUT3 D Q D Q D Q IN CLK 110 100 1 0 1 1 1 010 101 111 000 1 1 0 1 0 0 001 011 1 0 0 0 0 Can Any Sequential System be Represented with a State Diagram? • Shift Register • Input value shownon transition arcs • Output values shownwithin state node CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 21

    18. 010 011 001 000 100 3-bit up-counter 110 101 111 Counters are Simple Finite State Machines • Counters • Proceed thru well-defined state sequence in response to enable • Many types of counters: binary, BCD, Gray-code • 3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ... • 3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ... CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 22

    19. Verilog Upcounter module binary_cntr (q, clk) inputs clk; outputs [2:0] q; reg [2:0] q; reg [2:0] p; always @(q) //Calculate next state case (q) 3’b000: p = 3’b001; 3’b001: p = 3’b010; … 3’b111: p = 3’b000; endcase always @(posedge clk) //next becomes current state q <= p; endmodule CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 23

    20. OUT1 OUT2 OUT3 D Q D Q D Q CLK "1" How Do We Turn a State Diagram into Logic? • Counter • Three flip-flops to hold state • Logic to compute next state • Clock signal controls when flip-flop memory can change • Wait long enough for combinational logic to compute new value • Don't wait too long as that is low performance CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 24

    21. FSM Design Procedure • Start with counters • Simple because output is just state • Simple because no choice of next state based on input • State diagram to state transition table • Tabular form of state diagram • Like a truth-table • State encoding • Decide on representation of states • For counters it is simple: just its value • Implementation • Flip-flop for each state bit • Combinational logic based on encoding CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 25

    22. current state next state0 000 001 11 001 010 22 010 011 33 011 100 44 100 101 55 101 110 66 110 111 77 111 000 0 010 011 001 000 100 3-bit up-counter 110 101 111 FSM Design Procedure: State Diagram to Encoded State Transition Table • Tabular form of state diagram • Like a truth-table (specify output for all input combinations) • Encoding of states: easy for counters – just use value CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 26

    23. C3 C3 C3 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 1 C1 C1 C1 C2 C2 C2 C3 C2 C1 N3 N2 N10 0 0 0 0 10 0 1 0 1 00 1 0 0 1 10 1 1 1 0 01 0 0 1 0 11 0 1 1 1 01 1 0 1 1 11 1 1 0 0 0 N3 N1 N2 Implementation • D flip-flop for each state bit • Combinational logic based on encoding notation to show function represent input to D-FF N1 := C1' N2 := C1C2' + C1'C2 := C1 xor C2 N3 := C1C2C3' + C1'C3 + C2'C3 := C1C2C3' + (C1' + C2')C3 := (C1C2) xor C3 CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 27

    24. D Q Q Implementation (cont'd) • Programmable Logic Building Block for Sequential Logic • Macro-cell: FF + logic • D-FF • Two-level logic capability like PAL (e.g., 8 product terms) CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 28

    25. outputlogic Outputs Inputs next statelogic Next State Current State State Machine Model • Values stored in registers represent the state of the circuit • Combinational logic computes: • Next state • Function of current state and inputs • Outputs • Function of current state and inputs (Mealy machine) • Function of current state only (Moore machine) CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 34

    26. outputlogic Outputs Inputs next statelogic Next State Next State State Current State 0 1 2 3 4 5 Clock State Machine Model (cont’d) • States: S1, S2, ..., Sk • Inputs: I1, I2, ..., Im • Outputs: O1, O2, ..., On • Transition function: Fs(Si, Ij) • Output function: Fo(Si) or Fo(Si, Ij) CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 35

    27. Example: Ant Brain (Ward, MIT) • Sensors: L and R antennae, 1 if in touching wall • Actuators: F - forward step, TL/TR - turn left/right slightly • Goal: find way out of maze • Strategy: keep the wall on the right CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 36

    28. Ant Brain CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 37

    29. Ant Behavior B: Following wall, not touching Go forward, turning right slightly A: Following wall, touching Go forward, turning left slightly D: Hit wall again Back to state A C: Break in wall Go forward, turning right slightly E: Wall in front Turn left until... F: ...we are here, same as state B G: Turn left until... LOST: Forward until we touch something CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 38

    30. L + R L’ R LOST (F) E/G(TL) A (TL, F) L + R L R L’ R’ L’ R’ R L’ R’ B (TR, F) C(TR, F) R’ R’ Designing an Ant Brain • State Diagram CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 39

    31. Synthesizing the Ant Brain Circuit • Encode States Using a Set of State Variables • Arbitrary choice - may affect cost, speed • Use Transition Truth Table • Define next state function for each state variable • Define output function for each output • Implement next state and output functions using combinational logic • 2-level logic (ROM/PLA/PAL) • Multi-level logic • Next state and output functions can be optimized together CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 40

    32. L + R L’ R state L R next state outputs LOST 0 0 LOST F LOST – 1 E/G F LOST 1 – E/G F A 0 0 B TL, F A 0 1 A TL, F A 1 – E/G TL, F B – 0 C TR, F B – 1 A TR, F ... ... ... ... ... LOST (F) E/G(TL) A (TL, F) L + R L R L’ R’ L’ R’ R L’ R’ B (TR, F) C(TR, F) R’ R’ Transition Truth Table • Using symbolic statesand outputs CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 41

    33. Synthesis • 5 states : at least 3 state variables required (X, Y, Z) • State assignment (in this case, arbitrarily chosen) LOST - 000 E/G - 001 A - 010 B - 011 C - 100 state L R next state outputs X,Y,Z X', Y', Z' F TR TL 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 ... ... ... ... ... 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 ... ... ... ... ... it now remainsto synthesizethese 6 functions CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 42

    34. Synthesis of Next State and Output Functions state inputs next state outputs X,Y,Z L R X+,Y+,Z+ F TR TL 0 0 0 0 0 0 0 0 1 0 0 0 0 0 - 1 0 0 1 1 0 0 0 0 0 1 - 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 1 - 1 0 1 0 0 0 1 0 0 1 1 - 0 1 0 0 0 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 - 0 0 1 1 0 1 0 1 1 - 0 1 0 0 1 1 0 0 1 1 - 1 0 1 0 1 1 0 1 0 0 - 0 1 0 0 1 1 0 1 0 0 - 1 0 1 0 1 1 0 e.g. TR = X + Y Z X+ = X R’ + Y Z R’ = R’ TR CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 43

    35. F TR TL outputlogic next statelogic Next State L R X+ Y+ Z+ Current State X Y Z Circuit Implementation • Outputs are a function of the current state only - Moore machine CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 44

    36. Verilog Sketch module ant_brain (F, TR, TL, L, R) inputs L, R; outputs F, TR, TL; reg X, Y, Z; assign F = function(X, Y, Z, L, R); assign TR = function(X, Y, Z, L, R); assign TL = function(X, Y, Z, L, R); always @(posedge clk) begin X <= function (X, Y, Z, L, R); Y <= function (X, Y, Z, L, R); Z <= function (X, Y, Z, L, R); end endmodule CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 45

    37. L’ R’ L + R L’ R 000 (F) 001(TL) 010 (TL, F) L + R L 101 R L’ R’ R L’ R’ 011 (TR, F) 100(TR, F) 110 R’ 111 R’ Don’t Cares in FSM Synthesis • What happens to the "unused" states (101, 110, 111)? • Exploited as don't cares to minimize the logic • If states can't happen, then don't care what the functions do • if states do happen, we may be in trouble Ant is in deep trouble if it gets in this state CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 46

    38. State Minimization • Fewer states may mean fewer state variables • High-level synthesis may generate many redundant states • Two state are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same • Two conditions for two states to be equivalent: • 1) Output must be the same in both states • 2) Must transition to equivalent states for all input combinations CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 47

    39. L + R L’ R LOST (F) E/G(TL) A (TL, F) L + R L R L’ R’ L’ R’ R L’ R’ B (TR, F) C(TR, F) R’ R’ Ant Brain Revisited • Any equivalent states? CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 48

    40. L + R L’ R LOST (F) E/G(TL) A (TL, F) L + R L R L’ R’ L’ R’ L’ R’ B/C (TR, F) R’ New Improved Brain • Merge equivalent B and C states • Behavior is exactly the same as the 5-state brain • We now need only 2 state variables rather than 3 CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 49

    41. state inputs next state outputs X,Y L R X',Y' F TR TL 0 0 0 0 0 0 1 0 0 0 0 - 1 0 1 1 0 0 0 0 1 - 0 1 1 0 0 0 1 0 0 1 1 0 0 1 0 1 - 1 0 1 0 0 1 0 1 1 - 0 1 0 0 1 1 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 1 0 1 - 0 1 1 0 1 1 1 - 0 1 1 1 1 0 1 1 - 1 1 0 1 1 0 X X X X X TR Y+ TL X+ F 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 R R R R R L L L L L Y Y Y Y Y New Brain Implementation CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 50

    42. Sequential Logic Implementation Summary • Models for representing sequential circuits • Abstraction of sequential elements • Finite state machines and their state diagrams • Inputs/outputs • Mealy, Moore, and synchronous Mealy machines • Finite state machine design procedure • Deriving state diagram • Deriving state transition table • Determining next state and output functions • Implementing combinational logic CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 51