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Dynamic Scheduling

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  1. Dynamic Scheduling A scheme to overcome data hazards

  2. Advantages of Dynamic Scheduling • Dynamic scheduling - hardware rearranges the instruction execution to reduce stalls while maintaining data flow and exception behavior • It handles cases when dependences unknown at compile time • it allows the processor to tolerate unpredictable delays such as cache misses, by executing other code while waiting for the miss to resolve • It allows code that compiled for one pipeline to run efficiently on a different pipeline • It simplifies the compiler • Hardware speculation, a technique with significant performance advantages, builds on dynamic scheduling

  3. HW Schemes: Instruction Parallelism • Key idea: Allow instructions behind stall to proceedDIVD F0,F2,F4 ADDD F10,F0,F8SUBD F12,F8,F14 • Enables out-of-order execution and allows out-of-order completion(e.g., SUBD) • In a dynamically scheduled pipeline, all instructions still pass through issue stage in order (in-order issue) • Will distinguish when an instruction begins execution and when it completes execution; between 2 times, the instruction is in execution • Note: Dynamic execution creates WAR and WAW hazards and makes exceptions harder

  4. Dynamic Scheduling Step 1 • Simple pipeline had 1 stage to check both structural and data hazards: Instruction Decode (ID), also called Instruction Issue • Split the ID pipe stage of simple 5-stage pipeline into 2 stages: • Issue—Decode instructions, check for structural hazards • Readoperands—Wait until no data hazards, then read operands

  5. Tomasulo Algorithm • Control & buffers distributed with Function Units (FU) • FU buffers called “reservation stations”; have pending operands • Registers in instructions replaced by values or pointers to reservation stations(RS); called registerrenaming; • Avoids: WAR WAW hazards • More reservation stations than registers, so can do optimizations compilers cannot • Results to FU from RS, not through registers, over Common Data Busthat broadcasts results to all FUs • Load and Stores treated as FUs with RSs as well. • Integer instructions can go past branches, allowing FP ops beyond basic block in FP queue. RX inst. i RX  inst. j

  6. Tomasulo scheme From memory From instruction unit 6 5 4 3 2 1 FP Registers FP Operation queue Load buffers Operand buses Store buffers 3 2 1 Operation bus To memory 3 2 1 2 1 Reservation Stations FP Multipliers FP adders Common data bus (CDB)

  7. Reservation Station Components Op—Operation to perform in the unit (e.g., + or –) Vj, Vk—Value of Source operands • Store buffers has V field, result to be stored Qj, Qk—Reservation stations producing source registers (value to be written) • Note: No ready flags as in Scoreboard; Qj,Qk=0 => ready • Store buffers only have Qi for RS producing result Busy—Indicates reservation station or FU is busy Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register.

  8. Three Stages of Tomasulo Algorithm 1. Issue—get instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2. Execution—operate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3. Write result—finish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available • Normal data bus: data + destination (“go to” bus) • Common data bus: data + source (“come from” bus) • 64 bits of data + 4 bits of Functional Unit source address • Write if matches expected Functional Unit (produces result) • Does the broadcast

  9. Tomasulo Example Cycle 0

  10. Cycle: 0 From memory From instruction unit FP Registers 6 5 4 3 2 1 FP operation queue Load buffers Store buffers Operand buses 3 2 1 LD F6, 34(R2) Operation bus To memory 3 2 1 Reservation Stations 2 1 FP Multipliers FP adders Common data bus (CDB)

  11. Cycle: 1 From memory From instruction unit FP Registers 6 5 4 3 2 1 34+R2 F6 : load1 FP operation queue Load buffers Store buffers LD F2, 45(R3) Operand buses 3 2 1 LD F6, 34(R2) Operation bus To memory 3 2 1 Reservation Stations 2 1 FP Multipliers FP adders Common data bus (CDB)

  12. Cycle: 2 From memory From instruction unit FP Registers 6 5 4 3 2 45+R3 1 34+R2 F2 : load2 F6 : load1 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers LD F2, 45(R3) Operand buses 3 2 1 LD F6, 34(R2) Operation bus To memory 3 2 1 Reservation Stations 2 1 FP Multipliers FP adders Common data bus (CDB)

  13. Cycle: 3 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 45+R3 1 Mem[34+R2] F2 : load2 F6 : load1 SUB F8,F6,F2 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers LD F2, 45(R3) Operand buses 3 2 1 LD F6, 34(R2) Operation bus To memory 3 2 1 Reservation Stations 2 M load2 “F4” 1 FP Multipliers FP adders Common data bus (CDB)

  14. Cycle: 4 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 Mem[45+R3] 1 F2 : load2 DIVD F10,F0,F6 F6 : load1 F6 Mem[34+R2] SUB F8,F6,F2 F8: add1 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers LD F2, 45(R3) Operand buses 3 2 1 LD F6, 34(R2) L1: Mem[34+R2] Operation bus To memory L1: Mem[34+R2] L1: Mem[34+R2] 3 2 1 S load1 load2 Reservation Stations 2 M load2 “F4” 1 Mem[34+R2] FP Multipliers FP adders Common data bus (CDB)

  15. Cycle: 5 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F2  Mem[45+R3] F2 : load2 DIVD F10,F0,F6 F8: add1 SUB F8,F6,F2 F10: mult2 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers L2: Mem[45+R3] LD F2, 45(R3) Operand buses 3 2 1 Operation bus To memory L2: Mem[45+R3] L2: Mem[45+R3] 3 2 1 S Mem[R2] load2 Reservation Stations D Mult1 2 M load2 “F4” 1 Mem[45+R3] Mem[45+R3] Mem[45+R3] FP Multipliers FP Multipliers FP adders FP adders Common data bus (CDB)

  16. Cycle: 6 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F6: add2 DIVD F10,F0,F6 F8: add1 SUB F8,F6,F2 F10: mult2 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 A add1 M[R3] 1 S Mem[R2] M[R3] Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

  17. Cycle: 7 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F6: add2 DIVD F10,F0,F6 F8: add1 SUB F8,F6,F2 F10: mult2 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 A add1 M[R3] 1 S Mem[R2] M[R3] Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

  18. Cycle: 8 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F6: add2 DIVD F10,F0,F6 F8: add1 F8  M()-M() SUB F8,F6,F2 F10: mult2 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 A add1 M[R3] 1 S Mem[R2] M[R3] Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 M()-M() FP Multipliers FP adders Common data bus (CDB) Add1: M()-M()

  19. Cycle: 9 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F6: add2 DIVD F10,F0,F6 F10: mult2 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 A M()-M() M[R3] 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

  20. Cycle: 10 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F6: add2 DIVD F10,F0,F6 F10: mult2 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 A M()-M() M[R3] 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

  21. Cycle: 11 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 ADD F6,F8,F2 F6  (M()-m())+M() F6: add2 DIVD F10,F0,F6 F10: mult2 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 A M()-M() M[R3] 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB) Add2: (M()-M())+M()

  22. Cycle: 12 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 DIVD F10,F0,F6 F10: mult2 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

  23. Cycle: 13 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 DIVD F10,F0,F6 F10: mult2 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

  24. Cycle: 14 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 DIVD F10,F0,F6 F10: mult2 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

  25. Cycle: 15 From memory From instruction unit FP Registers F0 : mult1 6 5 4 3 2 1 DIVD F10,F0,F6 F10: mult2 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 FP Multipliers FP adders Common data bus (CDB)

  26. Cycle: 16 From memory From instruction unit FP Registers F0 : mult1 F0  M()*F4 6 5 4 3 2 1 DIVD F10,F0,F6 F10: mult2 FP operation queue Load buffers MULTD F0,F2,F4 Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D Mult1 M[R3] 2 M M[R3] “F4” 1 M()*F4 FP Multipliers FP adders Common data bus (CDB) Mult1: M()*F4

  27. Cycle: 17 From memory From instruction unit FP Registers 6 5 4 3 2 1 DIVD F10,F0,F6 F10: mult2 FP operation queue Load buffers Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D M()*F4 M[R3] 2 1 FP Multipliers FP adders Common data bus (CDB)

  28. Cycle: 57 From memory From instruction unit FP Registers 6 5 4 3 2 1 DIVD F10,F0,F6 F10: mult2 F10  M()*F4 / M() FP operation queue Load buffers Store buffers Operand buses 3 2 1 Operation bus To memory 3 2 1 Reservation Stations D M()*F4 M[R3] 2 1 FP Multipliers FP adders Common data bus (CDB) Mult2: M()*F4 / M()

  29. Tomasulo Example Cycle 1 Yes

  30. Tomasulo Example Cycle 2 Note: Unlike 6600, can have multiple loads outstanding

  31. Tomasulo Example Cycle 3 • Note: registers names are removed (“renamed”) in Reservation Stations; MULT issued vs. scoreboard • Load1 completing; what is waiting for Load1?

  32. Tomasulo Example Cycle 4 • Load2 completing; what is waiting for it?

  33. Tomasulo Example Cycle 5

  34. Tomasulo Example Cycle 6 • Issue ADDD here vs. scoreboard?

  35. Tomasulo Example Cycle 7 • Add1 completing; what is waiting for it?

  36. Tomasulo Example Cycle 8

  37. Tomasulo Example Cycle 9

  38. Tomasulo Example Cycle 10 • Add2 completing; what is waiting for it?

  39. Tomasulo Example Cycle 11 • Write result of ADDD here vs. scoreboard?

  40. Tomasulo Example Cycle 12 • Note: all quick instructions complete already

  41. Tomasulo Example Cycle 13

  42. Tomasulo Example Cycle 14

  43. Tomasulo Example Cycle 15 • Mult1 completing; what is waiting for it?

  44. Tomasulo Example Cycle 16 • Note: Just waiting for divide

  45. Tomasulo Example Cycle 55

  46. Tomasulo Example Cycle 56 • Mult 2 completing; what is waiting for it?

  47. Tomasulo Example Cycle 57 • Again, in-order issue, out-of-order execution, completion

  48. Tomasulo Drawbacks • Complexity • delays of 360/91, MIPS 10000, IBM 620? • Many associative stores (CDB) at high speed • Performance limited by Common Data Bus • Multiple CDBs => more FU logic for parallel assoc stores

  49. Tomasulo Loop Example Loop: LD F0 0 R1 MULTD F4 F0 F2 SD F4 0 R1 SUBI R1 R1 #8 BNEZ R1 Loop • Assume Multiply takes 4 clocks • Assume first load takes 8 clocks (cache miss?), second load takes 4 clocks (hit) • To be clear, will show clocks for SUBI, BNEZ • Reality, integer instructions ahead

  50. Loop Example Cycle 0