Chapter 5 Computer Systems Organization

1. Chapter 5Computer Systems Organization 國立雲林科技大學 資訊工程研究所 張傳育(Chuan-Yu Chang ) 博士 Office: ES 709 TEL: 05-5342601 ext. 4337 E-mail: chuanyu@yuntech.edu.tw

2. Outline • Introduction • The Von Neumann Architecture5.2.1 Memory and cache 5.2.2 I/O and Mass Storage 5.2.3 ALU 5.2.4 Control Unit 5.2.5 Putting All the Pieces Together • Historical Overview

3. Computer System Organization • Gates and circuits operate on the most elemental of data items, binary 0s and 1s • We need to look at higher-level components • Study computers as collections of functional units or subsystems. • Computer Organization -- Study computers in terms of their major functional units and how they work -- The concept of abstraction

4. The Concept of Abstraction • Figure 5.1 • Hierarchy of abstraction • 將圖(a)中的元件依功能群組成ABC三個block(圖b)。 • 我們只關心這些block執行的功能及如何連接。

5. Hierarchy of abstraction

6. The Von Neumann Architecture • Every computer in use today is based on a single design, they are based on the same fundamental principles. • The structure and organization of virtually all modern computers are based on a single theoretical model of computer design called the Von Neumann architecture

7. The Von Neumann Architecture (cont’d) • A model for designing and building computers that is based on the following three characteristics: • A computer constructed from four major subsystems called : memory, input/output, thearithmetic/logic unit(ALU), and the control unit(Fig. 5.2) • Thestored program concept • The instructions to be executed by the computer are represented as binary values and stored in memory. • The sequential execution of instructions • One instruction at a time is fetched from memory to the control unit, where it is decoded and executed.

8. The Von Neumann Architecture

9. Memory and Cache • Memory is the functional unit of a computer thatstores and retrieves the instructions and the data being executed. • Random Access Memory (RAM) has the following three characteristics:1. Divided into fixed-size units called cells, each cell is associated with a unique identified called address. 2. All access to memory are to a specified address, must fetch or store a complete cell 3. The time it takes to fetch or store a cell is the same for all cells in memory. • Read Only Memory (ROM) • Simply a random access memory unit. • The ability to store information has been disabled.

10. Structure of Random Access Memory

11. RAM • Cell size -- The number of bits per cell -- Or called memory width -- Non standard width – 6,8,12,16,24,30,32,36,48,60 -- Standard width – 8-bit unit, called a byte -- The largest unsigned integer value in a single cell is 11111111, that is 255. -- Multiple memory cells to store a single data value -- 2 or 4 bytes for one integer number -- 4 or 8 bytes for real number

12. Address of Cell • Each memory cell in a RAM is identified by a unique unsigned integer address 0,1,2,3,… • N bits to represent the address of a cell • So the range of addresses available from 0 ….. 2n-1 • 2n is called the maximum memory size or the address space of the computer • Address vs. the content of that address

13. Symbols

14. Memory Basic Operations • Two basic memory operations: • Fetch (address) • Fetch a copy of the content of the memory cell with the specified address and return those contents as the result of the operation • Original contents are unchanged • Nondestructive fetch • Store (address, value) • Store the specified value into the memory cell specified by address. The previous contents of the cell are lost. • Destructive store • Memory access time • The time to carry out either a fetch or a store operation. • Fetching and storing are allowed only to an entire cell.

15. Memory Registers • Two registers are used to implement the fetch and store operations, both operations require two operands: • Address • The address of the cell being accessed. • Value • The value stored operation /returned by the fetch operation. • MAR – Memory Address Register • Holds the address of the cell to be fetched or stored. • MDR – Memory Data Register • Contains the data value being fetched or stored.

16. Memory Registers(cont’d) • Fetch and store operations in a RAM • Fetch (address) • Load the address into the MAR • Decode the address in the MAR • Copy the contents of that memory location into the MDR • Store (address, value) • Load the address into the MAR • Load the value into the MDR • Decode the address in the MAR • Store the contents of the MDR into the memory location

17. Organization of Memory and Decoding Logic We can decode the address in the MAR using a decoder circuit.

18. Scalability • The problem with the memory organization shown in Fig. 5.5 is that it does not scale vary well, it could not be used to build a large memory unit. • Solution – two dimensional organization • The memory locations are stored in row major order • Each memory cell is connected to two selection lines, one called the row selection line, the other called the column selection line • Using two decoders instead of one decoder to choose the correct row and column selection lines.

19. Two-Dimensional Memory Organization Only the memory cell located at the intersection of these two selection lines will carry out a memory fetch or store operation. The two high-order bits are sent to the row decoder, the two low-order bits are sent to the column decoder

20. Fetch / Store Controller • To control whether memory does a fetch or a store operation, our memory unit needs one additional device called a Fetch/Store Control. • This unit determines whether we will put the contents of a memory cell into the MDR (a fetch operation) or put the contents of the MDR into a memory cell (a store operation)

21. Overall RAM Organization

22. Cache Memory • In Von Neumann model, only a single type of memory • Processor was sitting idle waiting for data or instructions to arrive • The memory access was becoming a bottleneck

23. Cache Memory (cont’d) • Principle of Locality • When the computer uses something, it will probably use it again very soon • The computer references a piece of data, it should also move that data from RAM to a special, high-speed memory unit called cache memory • A cache is 5 to 10 times faster than RAM but much smaller

24. The organization of the two-level memory hierarchy • When the computer needs a piece of information • Look first in cache to see whether the information needed is there • If it is not there, then access the desired information from RAM at the slower speed • Copy the data just fetched into the cache.

25. Cache Hit Rate • Example: • The information we need is in the cache 60% of the time, 60% is called the cache hit rate • 10 nsec for cache, 50 nsec for RAM • Average access time = (0.6*10) + 0.4*(10+50) = 30 nsec

26. Input/Output and Mass Storage • Input/Output (I/O) unit • The devices that allow a computer system to communicate and interact with the outside world and store information. • Human interfaces: monitor, keyboard, mouse • Archival storage: not dependent on constant power • Volatile memory • Information disappears when the power is turned off. e.g., RAM • Non-volatile storage • Information could be saved between shutdowns of themachine. e.g., disks,tapes. • There exist many different types of I/O systems.

27. I/O Devices • Two basic I/O device type • Human-readable • keyboards, screens, laser printers and so on. • Machine-readable (mass storage system) • floppy drives, hard disks, optical disks, CD-ROMs, and tapes. • Mass storage device comes in two distinct forms • Direct Access StorageDevices (DASD) • Sequential Access Storage Devices (SASD)

28. Input/Output and Mass Storage (continued) • Mass storage devices • Direct access storage device • Hard drive, CD-ROM, DVD, etc. • Uses its own addressing scheme to access data • Sequential access storage device • Tape drive, etc. • Stores data sequentially • Used for backup storage these days

29. Random Access vs. Direct Access • Remember the fundamental characteristics of random access: • Every memory cell has a unique address. • It takes the same amount of time to access every cell. • Direct access satisfies condition 1 butnot condition 2. • Every unit of information has a unique address, but the time needed to access that unit depends on its physical location and the current state of the device.

30. Sectors and Tracks • A disk stores information in units called sectors. • Each sector contains an address and a data block with a fixed number of characters. • A fixed number of sectors are placed on a concentric circle on the surface of the disk, called a track.

31. Organization of a typical disk

32. Disk Access Time • Disk access time consists of • Seek timeisthe time needed to position the read/write head over the correct track. • Latency is the time for the beginning of the desire sector to rotate under the read/write head. • Transfer time is time for the entire sector to pass under the read/write head and have its contents read into or written from memory.

33. Disk of Physical Characteristics • Rotation Speed=7200 rev/min =120 rev/sec= 8.33 msec/rev • Arm movement time=0.02 msec to move to an adjacent track • Number of tracks/surface =1000 (0 to 999) • Number of sectors/track =50 • Numbers of bytes/sector =512

34. Disk Access Time (table summarizes)

35. Sequential Access Storage Devices • Another type of mass storage device uses an access technique called sequential access. • A sequential access storage device behaves just like an audio cassette tape. • This type of backup operation fits the SASD model very well, and tape backup units are common storage devices on computer systems.

36. Input/Output Speed • Many I/O is very slow when compared to other components of a computer. • I/O controller : handles I/O event. • I/O buffer • A small amount of memory • I/O control and logic • To handle the mechanical functions of the I/O devices • Generate interrupt signal when an I/O operation is done.

37. Organization of the I/O Controller

38. The Arithmetic/Logic Unit • ALU(Arithmetic/Logic Unit) is the subsystem that performs such mathematical and logicaloperations as addition, subtraction, andcomparison for equality. • All modern machines the ALU and control units are integrated into a single component called the processor.

39. ALU Organization • The ALU is made up of three parts: • Registers • Register is a storage cell that holds the operands of an arithmetic operation or result. • Interconnections between the components • Bus: Data path • ALU circuitry

40. Registers • A register is a storage cell that hold the value of operands/results. • Similar to random access memory with the following differences: • Accessed by register designator • Faster than regular memory cell • They are not used for general-purpose storage but for specific purposes.

41. Multi-register ALU Organization 可用來儲存operand和result。

42. Using a Multiplexor Circuit to select the proper ALU result

43. Overall ALU Organization

44. Control Unit • The most fundamental characteristic of the von Neumann architecture is the stored program • A sequence of machine language instructions stored as binary values in memory. • The task of the control unit : • Fetch from memory the next instruction to be executed. • Decode instructions. • Execute the instruction by issuing the appropriate command to the ALU, memory and I/O controllers.

45. Machine Language Instructions • The operation code(shorthand op code )is a unique unsigned-integer code assigned to each machine language operation recognized by the hardware. • The address fields are the memory addresses of the values in which this operation will work. • N bits address has a maximum of 2N memory cell. • The number of address field in an instruction typically varies from 0 to 3.

46. Instruction Set • The set of all operations that can be executed by a processor is called its instruction set. • ReducedInstruction Set Computers (RISC) • Minimizes the amount of hardware circuitry needed to build a processor. • A program for a RISC machine may require more instruction more than CISC. • Complex Instruction Set Computers (CISC)

47. Machine Language (Assembly) • Machine language instructions can be grouped into four basic classes: • Data transfer • These are operations that move information between or within the different components of the computer. • Arithmetic/ logical • These are operations that cause the ALU to perform a computation. • Compare • These operations compare two values and set an indicator on the basis of the results of the compare. • Branch • Altering the normal sequential flow of control. • The decision whether to branch is based on the current settings of the condition codes.

48. Example of Simple Machine Language Instruction Sequences

49. Control Unit Registers and Circuits • The CU consists of three components: • Program counter • The program counter (PC) holds the address of the next instruction to be executed. • Instruction register • The instruction register(IR) holds a copy of the instruction fetched from memory. • Instruction decoder • To determine what instruction is in the IR, the op code portion of the IR must be decoded using an instruction decoder.

50. Organization of the Control Unit Registers and Circuits