Ethernet Bomber Ethernet Packet Generator for network analysis

1. Ethernet BomberEthernet Packet Generator for network analysis Final Presentation Oren Novitzky & Rony Setter Advisor: MonyOrbach Started: Spring 2008

2. Project Goals • Developing a hardware Ethernet packet generator for Ethernet networks benchmarking. • Support stand-alone operation with several user configurations. • Implementation of the system on Altera PCI-E Development kit board with Stratix II GX FPGA.

3. Project Goals • Learning common communication protocols such as Ethernet, UDP, IP • Learning HW development language and tools. • Building SW application to support and control the HW design.

4. Architecture guideline: • Hardware Optimization: - Accelerating the NIOS by implement large instruction/ data cache. - Using high speed external memory – DDR2 -Interfacing Altera’s TSE MAC with SGDMA (instead of NIOS II directly) - Increasing core clock from 100MHz to 166.67MHz using only one PLL.

5. Architecture guideline: • Software Optimization: -Using the UDP protocol (instead of TCP) to increase throughput performance - Networking with InterNiche’s “NicheStack” fully configurable networking stack and MicroC/OS-II operating system. - Raising compiler optimization level to maximum (3).

6. Block Diagram NIOS II terminal JTAG JTAG Debug Module PHY Marvell MII Ethernet MAC Altera TSE On chip Memory RJ-45 SGDMA Interface UDP/IP Packet generator External Ethernet 10/100 Mbps NicheStack UDP Networking NiosII DDR2 HP Controller + PLL @ 333MHz Ext. CLK 100MHz Flash HP Controller DDR2 SDRAM Flash memory

7. SOPC Architecture DDR2 Memory Controller JTAG UART NiosII Processor JTAG Debug Module On-chip Memory S S System Timer Inst M Data M S S S Avalon Main BUS (HS) Pipeline Bridge (LS) SGDMA TX S SGDMA RX Avalon Tristate S S Simple I/O Controllers FLASH Memory Controller S S Src Sink M Triple speed Ethernet MAC Sink Src S

8. SOPC Architecture

9. Software Design Overview • The application code is based on a template supplied by Altera for networking application designs (Simple Socket Server template). • The TSE device driver is also supplied by Altera and needs to be integrated to the software build in Nios II EDS library configuration. • Both the IP layer and the device driver are supplied by InterNiche Technologies. • Using third party WireShark 1.2.5 Network Protocol Analyzer (freeware) at the receiver station.

10. Software Structure – Thread Level Program main() Lower number = Higher priority benchmark_initial_task() Priority 1 NicheStack Tasks Benchmarking Application Task tk_netmain() Priority 2 tk_nettick() Priority 3 benchmark_driver() Priority 4

11. main() benchmark_initial_task() bmprint_menu() legal command? NO YES Software Structure – Code Level nios_get_command_string() NO iniche_net_ready bmcommand_from_console() udp_sender_plain() alt_iniche_init() YES netmain() udp_sender() print_test() bmprint_start() benchmark() benchmark_driver() socket() sendto() Delay? gettimeofday() YES waiting done? NO Calling NO Sending done? NO Flow YES YES print_result()

12. System Setup

13. Benchmarking Example - Transmitter

14. Benchmarking Example - Receiver

15. Benchmarking Example - Results

16. Benchmarking Example - Results

17. Benchmarking Example - Results

18. Benchmarking Example - Results

19. Conclusion • NetworkingPerformance • As published by Altera and InterNiche, reaching maximum link speed using this integrated design is doable, without the need of implementing the IP layer in HW. • Altera design suit and documentation • Although Altera’s documentation resources are almost endless, more than once we encountered mismatch between several documents (Quartus/NIOS/SOPC) • Future designs on this hardware platform • Our hardware platform consists of all the required features for future fast networking standalone designs