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EEL 5930 sec. 5, Spring ‘05 Physical Limits of Computing

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## EEL 5930 sec. 5, Spring ‘05 Physical Limits of Computing

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**http://www.eng.fsu.edu/~mpf**EEL 5930 sec. 5, Spring ‘05Physical Limits of Computing Slides for a course taught byMichael P. Frankin the Department of Electrical & Computer Engineering**Module #6 – Semiconductors & MOSFET Technology**A Brief Survey**Why Semiconductors?**• Conductors always have a high concentration of electrons in conduction bands • states that are free to move through the material • Insulators always have virtually zero electrons in such bands • conduction band energy is too high • all the electrons are stuck in valance bands • localized to particular atoms/molecules in the material • Semiconductors have a conduction band whose electron population is easily manipulated • Sensitive to dopants, applied potentials, temperature M. Frank, "Physical Limits of Computing"**Electronic Structure of Silicon**• Silicon, atomic number: 14 • s+p orbitals of shell 3 are (together) half full • Like in Carbon (element 6), s,p orbitals can rearrange to form four sp3 hybrid orbitals w. tetrahedral symmetry: • Each Si can share electrons with 4 neighboring Si’s to fill all the 3sp orbitals... Stable tetrahedral lattice, like diamond 1s 2s 2p 3s 3p M. Frank, "Physical Limits of Computing"**Electrons & Holes**• At normal temperatures, • a small percentage ofshell-3 electrons will be free of the bond orbitals • wandering thru the lattice… • leaving a “hole” in the lattice point they left • a hole acts like a positively charged particle • Once created, holes can “move,” too… • by a nearby electron hopping over to fill them • however, hole mobility is usually lower than that of electrons M. Frank, "Physical Limits of Computing"**Donor & Acceptor Dopants**• Boron (element 5) is one electron shy of having a half-empty shell 2 that would fit Si lattice • Boron atoms readily accept extra mobile electrons and lock them in place, forming a negative B- ion • Reduces free-electron concentration, increases hole concentration when implanted into silicon • Phosphorus (element 15) has one too many shell-3 electrons to fit in Si lattice • Donates the extra electronreadily to conduction band • Increases free-electron conc., decreases hole conc. 1s 2s 2p 3s 3p Forms P+ ion 1s 2s 2p 3s 3p M. Frank, "Physical Limits of Computing"**p-type vs. n-type Silicon**• Pure silicon: • Has an equal number of positive & negative charge carriers (holes & electrons, resp.) • Acceptor-doped (e.g., boron-doped) silicon: • Has a charge-carrier concentration heavily dominated by positive charge carriers (holes, h+) • Balanced by negative, immobile ions of acceptor atom • We call it a “p-type” semiconductor. • Donor-doped (e.g., phosphorus-doped) silicon • Has charge-carrier concentration heavily dominated by negative charge carriers (electrons, e-) • Balanced by positive, immobile ions of donor atom • Call it “n-type” semiconductor M. Frank, "Physical Limits of Computing"**pn junctions**P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- • What happens when you put p-type and n-type silicon in direct contact with each other? • Near the junction, electrons from the n and holes from the p diffuse into & annihilate each other! • Forms a depletion region free of charge carriers Depletion region p-type n-type h+ h+ h+ e- e- e- e- e- e- h+ h+ h+ h+ h+ h+ e- e- e- e- e- h+ h+ h+ h+ h+ e- e- e- h+ e- h+ e- e- h+ e- h+ h+ M. Frank, "Physical Limits of Computing"**pn junction electrostatics**P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ P+ B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- B- cf. Pierret ‘96 Depletion region p-type n-type h+ h+ h+ e- e- e- e- e- e- h+ h+ h+ h+ h+ h+ e- e- e- e- e- h+ h+ h+ h+ h+ e- e- h+ e- e- h+ e- e- h+ h+ + Charge density Electric field Built-involtage Electrostatic potential M. Frank, "Physical Limits of Computing"**npn MOSFET (n-FET)**Metal-Oxide-SemiconductorField-EffectTransistor Vbias gateelectrode n n p Potential as seenby electrons Electronpotentialenergy(negative ofelectricpotential) p+ p+ p+ p+ e e e e e e e e e p+ p+ p+ p+ e e e When Vbias > 0 e e e e e e e e e Gate voltage > Vt M. Frank, "Physical Limits of Computing"**CMOS Inverters**(a) CMOS inverter structure. (b) Transition curves. M. Frank, "Physical Limits of Computing"**Technology Scaling: Notation**• Historically, device feature length scales have decreased by ~12%/year. • So: feature length 0.88year : • 1/ (1/0.88)year 1.14 year : • up 14%/year • Meanwhile, typical CPU die diameters have increased by ~2.3%/year. (Less stable trend.) • Diameter 1.023year : • 1/Diameter 0.978year : • Quantities that are constant over time are written as 1 : M. Frank, "Physical Limits of Computing"**Resistance Scaling**• Fixed-shape wire (any shape):R /wt / = • All dimensions scalingequally. • E.g. a local interconnectin a small scaled logicblock / functional unit • Constant-length thin wire: R / = • Thin cross-chip wire: R / = ! • Up 33%/year! • Long-distance wires have to be extra thick to be fast • But, fewer thick wires can fit! t w Current flow M. Frank, "Physical Limits of Computing"**Capacitance Scaling**w • Fixed-shape structure (any):C w/s / = • E.g. scaled devices/wires • Per unit wire length: • C w/s / (constant) • Cross-chip thin wire: C • Per unit area: C /s • E.g., total on-chip cap./cm2 s M. Frank, "Physical Limits of Computing"**Some 1st-order Semiconductor Scaling Laws**• Voltages V (due to e.g. punch-through ) • Long-term: temperature T (prevents leakage) • Resistance: • Fixed-shape wire: R /wt / = • Thin cross-chip wire: R / = • Capacitance: • Fixed-shape structure: C w/s / = • Per unit wire length: C (constant) • Cross-chip wire: C • Per unit area: C 1/s M. Frank, "Physical Limits of Computing"**Why Voltage Scaling?**• For many years, logic voltages were maintained at fairly constant levels as transistors shrunk • TTL 5V logic – was standard for many years • later 3.3 V, now: ~1V within leading-edge CPUs • Further shrinkage w/o voltage scaling is no longer possible, due to various effects: • Punch-through • Device degradation from hot carriers • Gate-insulator failure • Carrier velocity saturation • In general, things break down at high field strengths • constant-field voltage scaling may be preferred M. Frank, "Physical Limits of Computing"**Punch-Through**Vbias gateelectrode n n p p+ p+ p+ p+ Zero bias e e e e e e e e e e e e Moderate bias e e e e e e Strong bias e e e e e e e e Very strong bias M. Frank, "Physical Limits of Computing"**Need for Voltage Scaling**Vbias gateelectrode n n p+ p+ p+ p+ e e e e e e p e e e e e e e e e e e e e e e e e e e e Vbias n n p p+ p+ p+ p+ e e e e e e e e e e e e e e e e e e e e e Smaller size & same voltage higher electric field strengths easier punch-through M. Frank, "Physical Limits of Computing"**Boltzmann Distribution**A • Consider a system B that is inter-acting thermally with a much larger system A. • Freely exchanging energy and information with it. • If the joint system AB is at thermal equilibirum, • Then ∂S/∂E = 1/Tif the system temperature is T. • Where S(E) is the maximum entropy of system A at energy E. • Suppose a small amount of energy dEmoves into subsystem B. • Then, system A loses entropy dS = dE/T. Goes from S, to S′ = S − dS. • The number of possible states of system A is: • Before losing the entropy: N = ?S = eS/k. • After losing the entropy: N′ = ?S′ = ?S − dS = e(S − dE/T)/k. • The ratio between the number of states “after” and “before” is: • If the “before” state is equilibrium (p → 1) then the “after” state has probability p′ = e−dE/kT. B Move slide to a thermo module. M. Frank, "Physical Limits of Computing"**Fermi-Dirac Distribution**• For indistinguishable particles that are subject to the Pauli exclusion principle (fermions), • For example, electrons, • The probability that a given single-fermion state at energy E is occupied is given by: • Where E is measured relative to the chemical potential μ (Fermi level) • Can be defined as the energy zero level E=0 where p = ½. • Note that as E→ ∞, p(E) → e−E/kT→ 0. • And as E → −∞, p(E) → 1 − e−|E|/kT→ 1. Move slide to a thermo module. M. Frank, "Physical Limits of Computing"**Bose-Einstein Distribution**• Gives the occupation numbern>0 (not just occupancy probability 0<p<1) of indistinguishable particles of a given type not subject to the Pauli exclusion principle (Bosons) in a state at energy E > 0 relative to the chemical potential μ. • Just like the Fermi-Dirac distribution, except for the sign in front of the 1 in the denominator. • Similarly, as E→ ∞, n(E) → p(E)→ e−E/kT→ 0. • As E → 0, n(E) → ∞. Move slide to a thermo module. M. Frank, "Physical Limits of Computing"**Move slide to a thermo module.**M. Frank, "Physical Limits of Computing"**Quantum Statistics & Currents**• Consider two alternative current trajectories thatdiffer in potential at somepoint by energy ∆E. • E.g., electrons crossing an on vs. off transistor. • The ratio between currents in the two cases is given by the ratio of occupation probabilities: • IH/IL = p(EH)/p(EL) = (exp[EL/kT]+1)/(exp[EH/kT]+1) • When both EL and EH are >>μ(Fermi level), • This simplifies to IH/IL = e−∆E/kT. • Therefore, ∆E = kT log (IL/IH). • E.g., IL/IH = 250M implies ∆E ≈ 20 kT ≈ 0.5 eV. EH “High road” H ∆E E EL “Low road” L x M. Frank, "Physical Limits of Computing"**Long-term Temperature Scaling?**• May be needed in the long term. • Sub-threshold power dissipation across “off” transistors is based on the leakage current density exp(−Vt / T) • Vt is the threshold voltage • Must scale down with Vdd, or else transistor can’t turn on! • Tis the thermal voltage at temperature T • Equal to kBT/q, where q is electron charge magnitude • Voltage spread of individual electrons fr. thermal noise • As voltages decrease, • leakage power will dominate • devices will become unable to store charge • Unless (eventually), T V • Only alternative to low T: Scaling halts! • Probably what must happen, because low temps.imply slow rate of quantum evolution. Unfortunately,lower T fewercharge carriers! M. Frank, "Physical Limits of Computing"**Delay Scaling**• Charging time delay t RC : • Through fixed shape conductor: RC = • Thin constant-length wire: RC • Via cross-die thin wire: RC · = up 36%/yr! • Through a transistor: RC · = • Implications: • Transistors increasingly faster than long thin wires. • Even becoming faster than fixed-shape wires! • Local communication among chip elements is becoming increasingly favored! M. Frank, "Physical Limits of Computing"**Performance scaling**• Performance characteristics: • Clock frequency for small, transistor-delay-dominated local structures: f 1/t (up 14%/yr) • Transistor density (per area): d = 1/ = • Perf. density RA = fd = ;chip area: A • Total raw performance (local transitions / chip / time): R = fd A = = 1.55year • Increases 55% each year! • Nearly doubles every 18 months (like Moore’s Law). • Raw performance has (in the past) been harnessed for improvements in serial microprocessor performance. • Future architectures will need to move to more parallel programming models to fully use further improvements. M. Frank, "Physical Limits of Computing"**Charges & Currents**• Charges & fields: • Charge on a structure: Q = CV • Surface charge density: Q/A • Electric field strengths: E = V/ • Currents: • Peak current densities: J = E/ • Peak current in a wire: I = JA • Channel-crossing times: t = /v • Due to constant e saturation velocity v 200 kmph • Current in an on-transistor: I = Q/t / = • Effective trans. on-resistance: R = V/I / = • ~4-20 kΩ is typical for a min-sized transistor Resistivity: Constant M. Frank, "Physical Limits of Computing"**Interconnect Scaling**• Since transistor delay dt scales as , • And wire delay dw (w. scaled cross-section size) for a wire of length scales as RC (/wt)(w/s) = 2/st 2/ = 2, • Then to keep dw < dt (1-cycle access) requires:2 < 2 < / = < 3/2 • So wire length in units of transistor length t is /t < 3/2/ = 1/2 (down 6%/year) • So number of devices accessible within a constant × dt in 2-D goes as (1/2)2 = , in 3-D as (1/2)3 = 3/2. • Circuits must be increasingly local. M. Frank, "Physical Limits of Computing"**Energy and Power**• Energy: • Energy on a structure: E QV CV2 2 = 3 • Energy per-area: EA CV2/A 3/2 = • Energy densities: E/3 3/3 (not a problem) • Power levels: • Per-area power: PA = EAf = (not a problem) • Power per die: P = PAA (up ~5%/year) • Power-per-performance: PA/RA = / = • But, if constant-field scaling is not used (and it has not been, very much, and cannot be much further) all the above scaling rates get increased by the square of the field strength (F) scaling rate. • Because V F·, and E and P scale with V2. M. Frank, "Physical Limits of Computing"**3-D Scalability?**• Consider stacking circuits in 3-D within a constant volume. • # of layers n: /thickness / • Total power: PT = P(flat chip)×n = • Enclosing surface area AE: • Power flux (if not recycled): PT/AE = / = • For this to be possible, coolant velocity &/or thermal conductivity must also increase as ! • Probably not feasible. • Power recycling is needed to scale in 3-D! M. Frank, "Physical Limits of Computing"**Types of Limits**• Meindl ‘95 identifies several kinds of limits on VLSI (from most to least fundamental): • Theoretical limits (focus on energy & delay) • Fundamental limits (such as we already discussed) • Material limits (dependent on materials used) • Device limits (dependent on structure & geometry) • Circuit limits (dependent on circuit styles used) • System limits (dependent on architecture & packaging) • Practical limits • Design limits • Manufacturing limits M. Frank, "Physical Limits of Computing"**Fundamental Limits**• Thermodynamic limits • Minimum dissipation per bit erasure • kT ln 2 limit. More stringent limits for reliability coming up. • Subthreshold conduction leakage currents • Ion/Ioff exp(Vdd / T) • Quantum mechanical limits • Tunneling leakage currents (cf. Mead ’94, next slide) • Energy-time uncertainty principle E h/t • Related to Margolus-Levitin bound tnop ≥ ½h/(E−E0) • Electromagnetic (relativistic) limits • Speed-of-light lower bound on delay for an interconnect of a given length, t≥ /c. M. Frank, "Physical Limits of Computing"**Tunneling Limit on Device Size**• This graph plots the de Broglie wavelength λ = h(2mE)−1/2 of electrons of effective mass m having kinetic energy equal to a given barrier height E. • This is alsothe min. barrier width neededto prevent electrons from tunneling with probability greater than 3.5×10−6. M. Frank, "Physical Limits of Computing"**Material Limits**• Carrier mobility (carrier velocity/field strength) • Affects carrier velocity, on-current, transition time • 6x higher in GaAs than in Si, but only at low field • Carrier saturation velocity (max velocity) • Nearly equal for Si and GaAs. • Velocity maxes out @ ~100 nm/ps • Occurs @ ~1-10 V/m in Si (depends on doping) • Breakdown field strength Ec • 33% higher in GaAs than Si • Thermal conductivity – next slide • Dielectric constants – slide after M. Frank, "Physical Limits of Computing"**Thermal Conductivity**• For a given (device+heat-sink) structure, P K T • P - rate of heat removal (power) • K - thermal conductivity of materials used • T - how much hotter is device than its surroundings • K is 3x lower in GaAs than in Si • Implies that GaAs is 3x slower than Si when speed is limited by conductive cooling through substrate (often true)! • Highest known K: Diamond! • K = 2 mW/m·K, 14 times higher than Silicon! • Can be a semiconductor if Boron-doped, or an insulator if not. • Also has high mobility, high breakdown voltage, & good tolerance for high-temperature operation. • NTT recently demonstrated a diamond semiconductor capable of 81 GHz frequencies in analog applications. • Apollo Diamond in Massachusetts is developing a cheap manufacturing capability for single-crystal diamond wafers using CVD. M. Frank, "Physical Limits of Computing"**Dielectric Constants**• Dielectric constants = /0 = C/C0. SiO2 4 • Want high in thin gate dielectrics, • To maximize channel surface-charge density, & thus on-current, for given VG,on, • But avoid very low thickness w. high tunneling leakage. • But, material must also be an insulator! (SrTi = 310!) • Want low for thick interconnect (“field”) insulators • To minimize parasitic C and delay of interconnects • Lowest possible is that of vacuum (1). Air is close. M. Frank, "Physical Limits of Computing"**Some Device Limits**• MOSFET channel length • Generally, the lower, the better! • Reduces load capacitance & thus load charging time. • But, lengths are lower-bounded by the following: • Manufacturing limits, such as lithography wavelengths. • Supply voltage lower-limits to keep a decent Ion/Ioff. • Depletion region thickness due to dopant density limits. • Yield, in the face of threshold variation due to statistical fluctuation in dopant concentrations. • Source-to-drain tunneling. • Distributed RC network response time • Limited by: • of wires (e.g. the recent shift from Al to Cu) • of insulators (at most, 4x less than SiO2 is possible) • Widths, lengths of wires: limited by basic geometry M. Frank, "Physical Limits of Computing"**Circuit Limits**• Power supply voltage limits (later) • Switching energy limits (later) • Gate delays: • Fundamentally limited by transistor characteristics, RC network charging times • each of which are limited as per previous slide • There is a fastest possible logic gate in any given device technology • esp. considering it has to be switched by similar gates • Static CMOS & its close relatives (precharged domino, NORA) are probably close to the fastest-possible gates using CMOS transistors in a given tech. generation. M. Frank, "Physical Limits of Computing"**System Limits**We’ll discuss these more later in the course… • Architectural limits • Power dissipation • Heat removal capability of packaging • Cycle time requirements • Physical size M. Frank, "Physical Limits of Computing"**Design & Design-Verification Limits**• Increasing complexity (# of devices/chip) leads to continual new challenges in: • Design organization • modularity vs. efficiency • Automatic circuit synthesis & layout • circuit optimization • Design verification • layout-vs-schematic • logic-level simulation • analog (e.g. SPICE) modeling • Testing and design-for-testability • test coverage M. Frank, "Physical Limits of Computing"**Manufacturing Limits**See the ITRS ‘01 roadmap for these. • Lithography resolution, tools • Dopant implantation techniques • Process changes for new device structures • Assembly & packaging • Yield enhancement • Environmental / safety / health considerations • Metrology (measurement) • Product cost & factory cost “Red brick wall” could be reached as early as 2006! --ITRS ‘03 M. Frank, "Physical Limits of Computing"**Possible Endpoints for Electronics**• Merkle’s minimal “quantum FET” • Mesoscale nanoelectronic devices based on metal or semiconductor “islands” • E.g. Single-electron transistors, quantum dots, resonant tunneling transistors. • Various organic molecular electronic devices • diodes, transistors • Inorganic atomic-scale devices • 1-atom-wide chains of conductor/semiconductor atoms precisely positioned on/in substrates • Also discuss: Superconducting devices M. Frank, "Physical Limits of Computing"**Energy Limits in Electronics**• Origin of CV2/2 switching energy dissipation • Thermal reliability bounds on CV2 scaling • Voltage limits • Capacitance limits • Leakage trends in MOSFETs M. Frank, "Physical Limits of Computing"**Limit on Switching Energy**• Consider temporarily connecting a single unknown bit to ground. • Average dissipation is 1/4 CV2. • At least T log 2 average dissipation is required to erase a bit by Landauer’s principle. • Therefore, CV2 4T log 2 = 4kBT ln 2. 0/1? 0 0 CV2/4 Entropy:log 2 Entropy:log 1 = 0 M. Frank, "Physical Limits of Computing"**Reliability w. Thermal Noise**• Consider N logic nodes, 1 of which is high. • Don’t know which: Entropy = log N. • Then, connect them all to ground temporarily. • Want them all to be 0, with high probability. • Logical entropy is now 0. • Log N entropy must be exported elsewhere. • Requires T log N expenditure of energy. • But, only ½CV2 energy was dissipated! • So, to reliably doNarbitrary irreversible bit operations requires at least½CV2 T log N = kBT ln N energy per logic node. M. Frank, "Physical Limits of Computing"**Illustration of Scenario**0 0 0 0 0 0 1 0 0 CV2/2 N 0 0 0 0 0 0 0 0 0 Entropy:0 Entropy:log N ½CV2 T log N M. Frank, "Physical Limits of Computing"