Intel 8086 Microprocessors

1. 8086 Intel 8086 Microprocessors • 8086 consists of two internal units • The execution unit (EU) - executes the instructions • The bus interface unit (BIU) - fetches instructions, reads operands and writes results • The 8086 has a 6B prefetch queue • The 8088 has a 4B prefetch queue

2. 8086 8086 Internal Organisation

3. 8086 8086 20-bit Addresses

4. 8086 8086 Addressing Modes • Implied Addressing Modes • Register and Immediate Addressing Modes • Memory Modes • I/O Addressing Modes • Relative Addressing Modes

5. 8086 Addressing modes • Implied - the data value/data address is implicitly associated with the instruction. Ex: HLT, CLC • Register - references the data in a register or in a register pair. Ex: MOV AX, CX • Immediate - the data is provided in the instruction. Ex: MOV AL, 08H • Direct - the instruction operand specifies the memory address where data is located. Ex:MOV CL, SS:12 • Register indirect - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers. Ex: MOV BX, SS[BP]

6. 8086 Addressing modes • Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides. • Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. • Based Indexed - the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. • Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides.

7. 8086 Addressing modes • I/O Addressing Mode – Used for I/O operations. 65536 8-bit I/O ports. These ports can be also addressed as 32768 16-bit I/O ports. Ex: OUT PORT_ADD, AL or OUT AL, PORT_ADD • Relative Addressing Mode –Jumps and CALL instructions. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 - -127 bytes from current instruction. Ex: JMP level_name

8. 8086 Instructions (list) ADD AND CALL CBW CLC CLD CMP CWD DEC DIV HLT IN INC INT IRET JMP NEG NOP NOT OR OUT POP POPF PUSH PUSHF LEA LOOP MOV MUL RCL RCR RET ROL ROR SAHF SHL SHR STC STD STI SUB TEST XCHG XOR

9. 8086 Instructions

10. 8086 Instructions

11. 8086 Instructions

12. 8086 Instructions

13. 8086 Instructions

14. 8086 Instructions

15. 8086 Instructions

16. 8086 Instructions

17. 8086 Instructions

18. 8086 Instructions

19. 8086 Instructions

20. 8086 8086 Microprocessor • 8086 microprocessors need support circuits in a microcomputer system • 8086 multiplex the address and data buses on the same pins • This saves pins but at a price: • Demultiplexing logic is needed to build up separate address and data buses to interface with RAMs and ROMs

21. 8086 8086 Microprocessor • Minimum Mode: • 8086 is configured to support small, single processor systems using a few devices that use the system bus • Maximum Mode: • 8086 is configured to support multi-processor systems. • 8086 needs at least the following: • 8288 Bus Controller, • 8284A Clock Generator, • 74HC373s and 74HC245s

22. 8086 Maximum Mode

23. 8086 8086 Maximum Mode • In maximum mode, the 8288 uses a set of status signals (S0, S1, S2) to rebuild the normal bus control signals of the microprocessor • MRDC#, MWTC#, IORC#, IOWC# etc • Equivalent to MEMR# etc • Look at some special signals briefly

24. 8086 RESET# Signal • The Active low RESET# signal puts the 8086 into a defined state • Clears the flags register, segment registers etc. • Sets the effective program address to 0FFFF0h (CS=0F000h, IP=0FFF0h) • 8086 Programs always start at 0FFFF0H after Reset has been asserted and removed • Continues into latest generation CPUs

25. 8086 BHE# Signal • The 8086 processor can address memory a byte at a time • Its data bus is 16 bits wide • It uses the BHE# signal and A0 (sometimes called BLE#) to address bytes using its 16b bus

26. 8086 Use of BHE#/A0(BLE#)

27. BHE# A0/BLE# Selection 8086 0 0 Whole word (16-bits) 0 1 High byte to/from odd address 1 0 Low byte to/from even address 1 1 No selection Use of BHE#/BLE#

28. 8086 ALE and Address/data Bus Multiplexing • 8086/8 Multiplexes the Address and Data signals onto the same set of pins • Need off-chip logic to separate the signals • Transparent latches designed just for address demultiplexing

29. 8086 ALE and 74HC373 Transparent Latch

30. 8086 Use of ALE (Address Latch Enable) • ALE is used with an external latch (74HC373) to demultiplex the address and data lines • 74HC373 is transparent when its LE input (connected to ALE) is high • When ALE goes low, the ‘373 holds the last data until ALE goes high again

31. 8086 8288 Bus Controller and Bus Transceivers

32. 8086 8086 Read Cycle

33. 8086 8086 Write Cycle

34. 8086 8086 Read Cycle (1 Wait State)

35. 8086 Summary • First Generation (introduced June 1978) • One of the first 16b processors on the market • 16b internal registers • 16/8b external data bus • 20b address bus (1MB addressable) • Used in 1st generation IBM PCs (1981)