Create Presentation
Download Presentation

Download Presentation

Biomedical Signal processing Chapter 6 structures for discrete-time system

Biomedical Signal processing Chapter 6 structures for discrete-time system

386 Views

Download Presentation
Download Presentation
## Biomedical Signal processing Chapter 6 structures for discrete-time system

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -

**Biomedical Signal processingChapter 6 structures for**discrete-time system Zhongguo Liu Biomedical Engineering School of Control Science and Engineering, Shandong University 山东省精品课程《生物医学信号处理(双语)》 http://course.sdu.edu.cn/bdsp.html 1 Zhongguo Liu_Biomedical Engineering_Shandong Univ.**§6 structures for discrete-time system**6.0 Introduction 6.1 Block Diagram Representation of Linear Constant-Coefficient Difference Equations 6.2 Signal Flow Graph Representation of Linear Constant-Coefficient Difference Equations 6.3 Basic Structures for IIR Systems 6.4 Transposed Forms 6.5 Basic Network Structures for FIR Systems**Structures for Discrete-Time Systems**6.0 Introduction**6.0 Introduction**Characterization of an LTI System: • Impulse Response • z-Transform: system function • Difference Equation →Frequency response • converted to a algorithm or structure that can be realized in the desired technology, when implemented with hardware. • Structure consists of an interconnection of basic operations of addition, multiplication by a constant and delay**Illustration for the IIR case by convolution**Example: find the output of the system with input x[n]. Solution1: IIR Impulse Response even if we only wanted to compute the output over a finite interval, it would not be efficient to do so by discrete convolution since the amount of computation required to compute y[n] would grow with n .**Example: find the output of the system**with input x[n]. Solution2: computable recursively The algorithm suggested by the equation is not the only computational algorithm, there are unlimited variety of computational structures (shown later).**Why Implement system Using Different Structures?**• Equivalent structures with regard to their input-output characteristics for infinite-precision representation, may have vastly different behavior when numerical precision is limited. • Effects of finite-precision of coefficients and truncation or rounding of intermediate computations are considered in latter sections. • Computational structures(Modeling methods): • Block Diagram • Signal Flow Graph**Structures for Discrete-Time Systems**6.1 Block Diagram Representation of Linear Constant-Coefficient Difference Equations**x2[n]**x1[n] a x1[n] + x2[n] + x[n-M] ax[n] x[n] M sample Delay z-M z1 x[n-1] x[n] 6.1 Block Diagram Representation of Linear Constant-Coefficient Difference Equations Three basic elements: Unit Delay (Memory, storage) Multiplier Adder**b0**+ z1 a1 + z1 a2 Ex. 6.1 draw Block Diagram Representation of a Second-order Difference Equation Solution: x[n] y[n] y[n-1] y[n-2]**Nth-Order Difference Equations**Form changed to a[0] normalized to unity**x[n]**y[n] b0 + + z1 z1 b1 a1 x[n-1] y[n-1] + + z1 z1 x[n-2] y[n-2] bM1 aN1 + + z1 z1 bM aN x[n-M] y[n-N] Block Diagram Representation(Direct Form I) v[n]**x[n]**y[n] b0 + + z1 z1 b1 a1 x[n-1] y[n-1] + + z1 z1 x[n-2] y[n-2] bM1 aN1 + + z1 z1 bM aN x[n-M] y[n-N] Block Diagram Representation(Direct Form I) v[n]**x[n]**y[n] b0 + + z1 z1 b1 a1 x[n-1] y[n-1] + + z1 z1 x[n-2] y[n-2] bM1 aN1 + + z1 z1 bM aN x[n-M] y[n-N] Block Diagram Representation(Direct Form I) Implementing zeros Implementing poles v[n]**y[n]**x[n] b0 + + z1 z1 b1 a1 x[n-1] y[n-1] + + z1 z1 x[n-2] y[n-2] bM1 aN1 + + z1 z1 bM aN x[n-M] y[n-N] Block Diagram Representation(Direct Form I) How many Adders? How many multipliers? How many delays? N +M N +M+1 N+M v[n]**x[n]**y[n] b0 + + z1 z1 b1 a1 x[n-1] y[n-1] + + z1 z1 x[n-2] y[n-2] bM1 aN1 + + z1 z1 bM aN x[n-M] y[n-N] Block Diagram Representation(Direct Form I) v[n]**x[n]**w[n] y[n] b0 + + z1 z1 a1 b1 w[n-1] + + z1 z1 w[n-2] aN1 bN1 + + z1 z1 aN bN w[n-N] Block Diagram Representation (Direct Form II) (or called Canonic direct Form) Assume M = N**x[n]**w[n] y[n] b0 + + z1 z1 a1 b1 w[n-1] + + z1 z1 w[n-2] Assume M = N aN1 bN1 + + z1 z1 aN bN w[n-N] Block Diagram Representation (Direct Form II)**x[n]**w[n] y[n] b0 + + z1 z1 a1 b1 w[n-1] + + z1 z1 w[n-2] aN1 bN1 + + z1 z1 aN bN w[n-N] Block Diagram Representation (Direct Form II) Implementing poles Implementing zeros Assume M = N**x[n]**w[n] y[n] b0 + + z1 z1 a1 b1 w[n-1] + + z1 z1 w[n-2] Assume M = N aN1 bN1 + + z1 z1 aN bN w[n-N] Block Diagram Representation (Direct Form II) N +M How many Adders? How many multipliers? How many delays? N +M+1 N+M**x[n]**y[n] b0 + + z1 a1 b1 + + z1 Assume M = N aN1 bN1 + + z1 aN bN Block Diagram Representation (Canonic Direct Form or direct Form II) How many Adders? How many multipliers? How many delays? max(M, N) N +M N +M+1 N**v[n]**1 x[n] y[n] + + z1 z1 2 1.5 y[n-1] + x[n-1] z1 0.9 y[n-2] x[n] w[n] 1 y[n] + + z1 2 1.5 + w[n-1] z1 0.9 w[n-2] Ex. 6.2 draw Direct Form Iand Direct Form IIimplementation of an LTI system Solution:**Structures for Discrete-Time Systems**6.2 Signal Flow Graph(信号流图) Representation of Linear Constant-Coefficient Difference Equations**wj[n]**wk[n] Node k Node j 6.2 Signal Flow Graph Representation of Linear Constant-Coefficient Difference Equations • A Signal Flow Graph is a network of directed branches(有向支路)that connect at nodes(节点). Associated with each node is a variable or node value, being denoted wj[n]. 梅森(Mason)信号流图**Nodes And Branches**We will only consider linearSignal Flow Graph Output:A linear transformation of input, such as constant gain and unit delay. Input wj[n] if omitted, it indicates unity a or z-1 Brach (j, k) wj[n] wk[n] Node j Node k Each branch has an input signal and an output signal. An internal node serves as a summer, i.e., its value is the sum of outputs of all branches entering the node.**Sink node k**Source node j wj[n] yk[n] xj[n] wk[n] Source Nodes (源点 ) • Nodes that have no entering branches Sink Nodes (汇点 ) • Nodes that have only entering branches**d**a w2[n] b e w1[n] y[n] x[n] c Example : determine Linear Constant-Coefficient Difference Equations of SFG Sink Node Source Node Solution:**b0**+ + z1 b1 a b0 2 3 b1 1 a 4 Block Diagram vs. Signal Flow Graph w[n] y[n] x[n] branching point Canonic direct Form Source Node Sink Node w1[n] x[n] y[n] w2[n] w3[n] Delay branch By convention, variables is represented as sequences rather than as z-transforms z1 w4[n] =w2[n-1] Delay branch cannot be represented in time domain by a branch gain by z-transform, a unit delay branch has a gain of z-l.**b0**+ + z1 b1 a b0 1 2 3 z1 a b1 4 Block Diagram vs. Signal Flow Graph Determine the difference equation (System Function) from the Flow Graph. Solution: x[n] w[n] y[n] w1[n] x[n] y[n] w2[n] w3[n] w4[n]**Block Diagram vs. Signal Flow Graph**Determine difference equation difficult in time-domain**Ex. 6.3 Determine the System Function from Flow Graph**Solution:**Ex. 6.3 Determine the System Function from Flow Graph**for causal system :**a**-a x[n] y[n] z-1 z-1 Ex. 6.3 compare two implementation requires only one multiplication andone delay (memory) element direct form I implementation twomultiplication andtwo delay**Structures for Discrete-Time Systems**6.3Basic Structure for IIR Systems**6.3Basic Structure for IIR Systems**• for a rational system function, many equivalent difference equationsor network structures exists. one criteriain the choice among these differentstructures is computational complexity: • Reduce the number of constant multipliers • Increase speed • Reduce the number of delays • Reduce the memory requirement • others: VLSI design;Modularity; multiprocessor implementations; effects of a finite register length and finite-precision arithmetic**Basic Structures for IIR Systems**• Direct Forms • Cascade Form • Parallel Form**b0**x[n] y[n] + + z1 z1 b1 a1 x[n-1] y[n-1] + + z1 z1 x[n-2] y[n-2] bM1 aN1 + + z1 z1 bM aN x[n-M] y[n-N] 6.3.1 Direct Forms v[n]**x[n]**y[n] v[n] b0 + + z1 z1 a1 b1 y[n-1] x[n-1] + + z1 z1 x[n-2] y[n-2] bM1 aN1 + + z1 z1 bM aN y[n-N] x[n-M] v[n] b0 x[n] y[n] z1 z1 a1 b1 x[n-1] y[n-1] z1 z1 b2 a2 y[n-2] x[n-2] bN-1 aN-1 y[nN+1] x[nM+1] z1 z1 bN aN x[n-M] y[n-N] Direct Form I Block Diagram Signal Flow Graph**v[n]**x[n] b0 y[n] z1 z1 a1 b1 x[n-1] y[n-1] z1 z1 b2 a2 y[n-2] x[n-2] bN-1 aN-1 y[nN+1] x[nM+1] z1 z1 aN bN x[n-M] y[n-N] Direct Form I Signal Flow Graph**w[n]**y[n] x[n] b0 z1 a1 b1 z1 a2 b2 aN-1 bN-1 z1 aN bN Direct Form II**w[n]**y[n] x[n] b0 z1 b1 a1 z1 b2 a2 bN-1 aN-1 z1 bN aN Direct Form II**x[n]**y[n] z1 z1 z1 z1 y[n] x[n] z1 z1 Ex. 6.4 draw Direct Form I andDirect Form II structures of system Solution: 0.75 2 Direct Form I 0.125 2 0.75 Direct Form II 0.125**6.3.2 Cascade Form(串联形式)**when all the coefficients are real 1st-order factors represent real zeros at gkand real poles at ck , and the 2nd-order factors represent complex conjugate pairs of zeros at hk and h*k and poles at dk ,d*k**2nd Order**System 2nd Order System 2nd Order System Cascade Form A modular structure**b01**b02 b03 z1 z1 z1 a11 b11 a12 b12 a13 b13 z1 z1 z1 a21 b21 a22 b22 a23 b23 Cascade Form For example, assume Ns=3 x[n] y[n] 1 2 3 It is used when implemented with fixed-point arithmetic, the structure can control the size of signals at various critical points because they make it possible to distribute the overall gain of the system.**x[n]**y[n] z1 2 0.75 Direct Form II z1 0.125 Ex. 6.5 draw the Cascade structures Solution: 1st-order Direct Form I 1st-orderDirect Form II**z1**z1 z1 a11 b11 a12 b12 a13 b13 z1 z1 z1 a21 b21 a22 b22 a23 b23 Another Cascade Form implemented with fixed-point arithmetic used to decrease the amount of computation, when floating-point arithmetic is used and dynamic range is not a problem. b0 x[n] y[n] ~ ~ ~ ~ ~ ~**Parallel Form**Complex Poles Poles at zero Real Poles Group Real Poles in pairs**Ckz-k**C0 e0k x[n] y[n] z1 a1k e1k z1 a2k Parallel Form