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The Design of a ISA DSP CARD. by Asher C. Martin Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign Tel: 217-367-3877 e-mail: martin2@uiuc.edu. “Nothing is particularly hard if you divide it into small jobs.” -Henry Ford-.

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the design of a isa dsp card

The Design of aISA DSP CARD

by Asher C. Martin

Department of Electrical and Computer Engineering

University of Illinois at Urbana-Champaign

Tel: 217-367-3877

e-mail: martin2@uiuc.edu

project goals introduction
Project Goals & Introduction
  • Design of an embedded DSP system from the ground up
  • DSP card would meet a variety of practical real-world applications
  • High-speed digital signal processing
design specs
Design Specs
  • DSP I/O Performance:
    • ADC: 16 bit input resolution at 85 ksps (~76μV)

(thousands of samples per-second)

    • DAC: 8 bit output resolution
  • Three FPGA’s (run in “parallel” x 3)
    • 25 MHz 
    • Total of 30 thousand reprogramable gates
  • ISA BUS Performance:
    • 8 MHz with 8 bit transfers
  • 252 + interconnections with nearly 150 ft of wire wrap
block diagram
Block Diagram

SRAM

ADC/DAC

DSP

ISA

how did i test the card
How did I test the card?
  • With nearly 150 ft of wire on a board testing the various components was difficult.
  • Used the model “keep it simple” and divide my system into the DSP, ISA, and SRAM interfaces.
how does the dsp work
How does the DSP work?
  • The DSP is interfaced with all of the other components on the card.
  • Memory Address Bus - 8 bit (with SRAM)
  • Memory Data Bus - 8 bit (with SRAM)
  • Host PC Data Bus - 8 bit (with ISA BUS)
  • OPCODE Bus - 8 bit (with all FPGA’s)
  • Two Custom DSP ports
    • Analog Port (9 pin / Port A)
    • Digital Port (26 pin / Port B)
dsp layout
DSP Layout

SRAM/ISA

DATA BUS

SRAM ADDRS

ADC/DAC

INTERFACE

DSP FPGA

physical dsp interface

TWO CUSTOM

DSP PORT

Physical DSP Interface

ADC

SRAM/ISA

DATA BUS

isa bus interface
ISA Bus Interface
  • Address Bus - 12 bit (with host PC)
  • Data Bus - 8 bit (with host PC)
  • “inp/outp” port 380h
    • (with host PC software)
    • I/O Address is reprogramable
physical isa bus interface
Physical ISA Bus Interface

12 Bit Address

8 Bit Data

interfacing with the sram
Interfacing with the SRAM
  • Since I couldn’t purchase SRAM from Cypress I had to make my own RAM inside the FPGA.
  • Address Bus
    • 8 bit with DSP
  • Data Bus
    • 8 bit with DSP

DATA BUS

ADDRESS BUS

sram interface
SRAM Interface

ADDRESS

DATA

dsp software gui
DSP Software (GUI)

RECIEVE

TRANSMIT

concluding remarks future
Concluding Remarks / Future
  • “...divide it into small jobs.” -Henry Ford-
  • Future Additions:
    • IRQ: Interrupt based I/O with ISA bus
    • 16 bit ISA I/O transfers
    • High-performance FPGA’s (200Mhz +)
    • Improve accuracy of ADC by separating digital and analog grounds.
references
References
  • Maxim IC (datasheets)
    • http://www.maxim-ic.com
  • Xilinx (hardware/software)
    • http://www.xilinx.com
  • ECE Stores
    • Components suggestions
  • Lawrence Ronk (ECE 345 TA)
    • ronk@ews.uiuc.edu