“Embedded” RAMP Workshop. 8/23/06 bee2.eecs.berkeley.edu/wiki/embedded. 100-1000 Core CMPs. RAMP Project. 1-10 Core SoCs. 1M Processor SuperComputers. Schedule:. 10:00-10:15 Introductions, etc. 10:15-11:00 Wawrzynek, Asanovic (UCB) RAMP Vision and Infrastructure
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10:00-10:15 Introductions, etc.
10:15-11:00 Wawrzynek, Asanovic (UCB)
RAMP Vision and Infrastructure
11:00-11:30 Uli Ramacher (Infineon)
Mass Mark Applications Driving MPSoC and Design Challenges
11:30-12:00 Ulrich Ruecker (HNI, Paderborn University)
High-level Desc. of Instructions Sets and Compi. Generation
12:00-12:30 Wolfgang Raabs (Infineon)
Virtual Prototype and Design Flow
1:30-2:00 Kurt Keutzer (UCB)
Mapping task graphs to processors in large multiprocessor systems
2:00-2:30 Chen Chang (BEECube)
Hardware and Tools for Architecture Exploration
2:30-3:30 Free Discussion