slide1 n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
ITRS Table Definitions/Guidelines, Proposal Rev1, 7/11/00 PowerPoint Presentation
Download Presentation
ITRS Table Definitions/Guidelines, Proposal Rev1, 7/11/00

Loading in 2 Seconds...

play fullscreen
1 / 42

ITRS Table Definitions/Guidelines, Proposal Rev1, 7/11/00 - PowerPoint PPT Presentation


  • 143 Views
  • Uploaded on

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'ITRS Table Definitions/Guidelines, Proposal Rev1, 7/11/00' - cais


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
slide1

ITRS/ORTC Table UpdateTechnology Node, DRAM Chip Size, and Logic Chip Size Update, Based on the IRC “Best Case Opportunities” Proposal, 7/11ITRS 2000 UpdateRev 1ke, 7/28/00Rev 1kb: 1) New Definition wording proposal Rev 1; 2) Document 7/11 IRC Technology Node decisions ; 3) Chip sizes updated to new “Best Case” aggressive technology node impact; 4) Other TWG table line items impact Proposal added (Pin Count, Frequency, Voltage/Power, Defect Density, Cost) 4) ongoing misc. correctionsContact: Alan Allan 480-554-8624, alan.k.allan@intel.com

ITRS 2000 Update Work In Progress - Do Not Publish!

slide2

ITRS Table Definitions/Guidelines, Proposal Rev1, 7/11/00

White

Red

Yellow

  • Technology Requirements Perspective

- Near-Term Years : First Yr. Ref.+ 6 yrs F’cast (ex. 1999 through 2005), annually

- Long-Term Years : Following 9 years (ex.: 2008, 2011, and 2014), every 3 years

  • Technology Node :

- General indices of technology development.

- Approximately 70% of the preceding node, 50% of 2 preceding nodes.

- Each step represents the creation of significant technology progress

- Example:DRAM half pitches (2000 ITRS) of 180, 130, 90, 65, 45 and 33 nm

*Year 2000 : Smallest 1/2 pitch among DRAM, ASIC, MPU, etc

  • Year of Production:

- The volume =*10K units (devices)/month. ASICs manufactured by same

process technology are granted as same devices

- Beginning of manufacturing by*a company and another company starts

production within 3 months  

  • Technology Requirements Color :

- : ManufacturableSolutions are NOT known

- : ManufacturableSolutions are known

- : Manufacturable Solutions exist, and they are being optimized

*Year 2000 : Red cannot exist in next 3 years (2000, 2001, 2002)**

*Year 2000 : Yellow cannot exist in next 1 year (2000)

** Exception: Solution NOT known, but does not prevent Production manufacturing

ITRS 2000 Update Work In Progress - Do Not Publish!

summary of key assumption proposed changes was 1999 itrs vs is best case proposal technology node
Summary of Key Assumption Proposed Changes WAS(1999 ITRS) vs. IS(“Best Case” Proposal) (Technology Node):

Technology Node Assumptions (per IRC Proposal 7/11/00):

a) DRAM Half-Pitch:

WAS: 3-year Node cycle (0.7x/3yrs), except year 2005 shifted off trend

IS [2]: 130nm pull-in to 2001 and ~.7x/3yrs(.5x/6yrs) reduction rate, rounded to nearest 5nm

WAS (nm): 1999/180, 2000/165, 2001/150, 2002/130, 2003/120, 2004/110, 2005/100; 2008/70, 2011/50, 2014/35

IS (nm): 1999/180, 2000/150, 2001/130, 2002/115, 2003/100, 2004/90, 2005/80; 2008/60, 2011/40, 2014/30

Note: .7x/Node(.5x/2 Nodes): 2001/130; 04/90; 07/65; 10/45; 13/33; 16/23

b) MPU/ASIC Half-Pitch:

WAS: MPU/ASIC Half-Pitch Same, lagged typically 1-2 years behind DRAM

IS [tied to DRAM[2] ]: pull-in one year starting 160nm in 2001, then ~.7x/3yrs(.5x/6yrs) reduction rate, rounded to nearest 5nm

WAS: 1999/230, 2000/210, 2001/180, 2002/160, 2003/145, 2004/130, 2005/115; 2008/80, 2011/55, 2014/40

IS: 1999/230, 2000/190, 2001/160, 2002/145, 2003/130, 2004/115, 2005/100; 2008/70, 2011/50, 2014/35

ITRS 2000 Update Work In Progress - Do Not Publish!

slide4
Summary of Key Assumption Proposed Changes WAS(1999 ITRS) vs. IS/NEW(“Best Case” Proposal) (Technology Node):

Technology Node Assumptions (cont.):

c) MPU/ASIC “In Resist” Gate Length:

WAS: MPU Gate Length 2-year node cycle (.7x/2yrs) to 2001, then 3-year node cycle (.7x/3yrs); ASIC Gate Length typically lagged ~1 node behind MPU

IS: 1. MPU Same as 1999 ITRS, except Variable ranges in 2002, 2011, 2014 replaced by single targets; 2. ASIC same as MPU

WAS (nm): MPU: 1999/140 , 2000/120, 2001/100, 2002/85-90, 2003/80, 2004/70, 2005/65; 2008/45, 2011/30-32, 2014/20-22

ASIC: 1999/180 , 2000/165, 2001/150, 2002/130, 2003/120, 2004/110, 2005/100; 2008/70, 2011/50, 2014/35

IS (nm): MPU/ASIC: 1999/140 , 2000/120, 2001/100, 2002/90, 2003/80, 2004/70, 2005/65; 2008/45, 2011/33, 2014/23

d) NEW: MPU/ASIC “Physical Bottom” Gate Length line item targets added which are pulled-in 1 year from the Lithography “In Resist” targets.

NEW (nm): 1999/120, 2000/100, 2001/90, 2002/80, 2003/70, 2004/65, 2005/60; 2008/40, 2011/30, 2014/20

ITRS 2000 Update Work In Progress - Do Not Publish!

slide5

=> Roadmap portion still under discussion

ITRS 2000 Update Work In Progress - Do Not Publish!

slide6

=> Roadmap portion still under discussion

ITRS 2000 Update Work In Progress - Do Not Publish!

itrs roadmap acceleration continues including mpu asic physical gate length proposal

95

97

99

01

04

07

10

13

500

* Note: MPU ASIC Physical Bottom Gate Length Preliminary 2000 Update TWG table targets are still under discussion.

1994

350

250

1997

Technology Node

180

1998

130

1999

and MPU/ASIC Gate Length Minimum Feature Size (nm)

2000

Proposal

Technology Node - DRAM Half-Pitch (nm)

XXX90

100

Minimum Feature

XX65

70

MPU/ASIC Gate “Physical”

XX45

50

7/11 IRC Proposal - Best CaseOpportunities*

MPU/ASIC Gate “In Resist”

XX 33

35

DRAM Half Pitch

XX 23

25

01

97

99

04

95

10

13

07

Year of Production

~.7x per technology node (.5x per 2 nodes)

ITRS Roadmap Acceleration Continues...(Including MPU/ASIC “Physical Gate Length” Proposal)

ITRS 2000 Update Work In Progress - Do Not Publish!

summary of key assumption proposed changes was 1999 itrs vs is best case proposal cont dram
Summary of Key Assumption Proposed Changes WAS(1999 ITRS) vs. IS(“Best Case” Proposal) (cont.- DRAM):

DRAM Assumptions:

a) Cell Area Factor Limits (from FEP TWG):

WAS: 8x/1999 -> 6x/2002 -> 4.4x/2005 -> 3.0x/2011 -> 2.5x/2014

IS: 8x/1999-2004, 6x/2005-2010, 4x/2011-16

b) Cell Array Efficiency Limit Trends (from FEP, Nikkei Microdevices):

WAS: Intro: 1999/70% --> 2016/75%

IS: Intro: 1999/70% --> 2016/75%

WAS: Production 1999/53% --> 2016/57%

IS: Production 1999/53% --> 2016/58%

c) Litho Field Size Maximum Limit (from Litho TWG):

WAS: 4x Magnification, 6-inch Reticle

Intro 1999-2016 25x32 = 800mm2

Production 1999-2016 12.5x32 = 400mm (2 chips/field)

IS: 5x Magnification, 6-inch Reticle

Intro 1999-2016 22x26 = 572mm2

Production 1999-2016 11x26 = 286mm2 (2 chips/field)

d) Bits/Chip Product Generation Growth Rate:

WAS: 1999-2014: 2x bits/chip every 2 years

IS: @ Introduction: Through 8Gbit: 2x bits/chip every 2 years;

After 8Gbit: 2x bits/chip every 2-3 years (4x/5years)

@ Production: Through 32Gbit: 2x bits/chip every 2 years;

After 32Gbit: 2x bits/chip every 2-3 years (4x/5years)

ITRS 2000 Update Work In Progress - Do Not Publish!

summary of key assumption proposed changes was 1999 itrs vs is is best case proposal cont logic
Summary of Key Assumption Proposed Changes WAS(1999 ITRS) vs. IS IS(“Best Case” Proposal) (cont.- Logic):

MPU Assumptions:

a) High Performance (HP) MPU @Ramp Starting Chip Size:

WAS: 2Mbyte on-chip (6t) SRAM in 1999

(170mm2 Core plus 280mm2 SRAM = 450mm2/1999)

IS: 1Mbyte on-chip (6t) SRAM in 1999

(170mm2 Core plus 140mm2 SRAM = 310mm2/1999)

b) Cost Performance (CP) Starting Chip Size (SAME as 1999 ITRS):

MPU @Introduction/340mm2

MPU @Ramp/170mm2

c) SRAM and Logic Transistors/chip Trend (SAME as ITRS) = 2x/2yrs

d) Chip Size Growth Rate Trend

WAS/ IS(7/11): Flat chip sizes through 2001, then 1.2x/4rs

ITRS 2000 Update Work In Progress - Do Not Publish!

slide10

Chip Size - Model Assumptions, Notes, Tables

ITRS 2000 Update Work In Progress - Do Not Publish!

slide11

Chip Size - Model Assumptions, Notes, Tables (cont. - MPU)

ITRS 2000 Update Work In Progress - Do Not Publish!

slide12

Part 2 -

DRAM Tables

Rev 1ke, 7/28/00

( §Note that target node years are now proposed to be: 1999/180nm; 2001/130nm; 2004/90nm; 2007/65nm; 2010/45nm; 2013/33nm; 2016/23nm)

ITRS 2000 Update Work In Progress - Do Not Publish!

slide18

DRAM - ORTC Chip Size Model Per IRC Technology Node Proposal [IS, 7/11/00] (cont):

ITRS 2000 Update Work In Progress - Do Not Publish!

slide19

MPU/ASIC Tables

ITRS 2000 Update Work In Progress - Do Not Publish!

slide20

MPU/ASIC Tables

- Functions/Chip

- Chip Size

- Density

ITRS 2000 Update Work In Progress - Do Not Publish!

slide26

MPU/ASIC (M/A) - ORTC Chip Size Model Per IRC Technology Node Proposal [IS, 7/11/00] (cont):

ITRS 2000 Update Work In Progress - Do Not Publish!

slide27

Part 3 -

Other ORTC Table TWG Line Items

Rev 1ke, 7/28/00

( §Note that actual node years are now proposed to be: 1999/180nm; 2001/130nm; 2004/90nm; 2007/65nm; 2010/45nm; 2013/33nm; 2016/23nm)

ITRS 2000 Update Work In Progress - Do Not Publish!

slide28

Other ORTC Table TWG Line Items

- Table 2a,b Litho Field Size Litho

Wafer Size FEP, FI

- Table 3a,b # of Chip I/O’s Test, Design

# of Package Pins/Balls Test, A&P

- Table 4a,b Chip Pad Pitch A&P

Cost-Per-Pin A&P

Chip Frequency Design

Max # Wire Levels Interconnect

- Table 5a,b Electrical Defects Def. Reduct.

- Table 6a,b P.Supply Volt. PIDs

Max. Power Design, PIDs

- Table 7a,b Affordable Cost Economic (AA actg)

Test Cost Test

ITRS 2000 Update Work In Progress - Do Not Publish!