Production Readiness Review

1. Production Readiness Review • Welcome! • Our motto: When you earnestly believe you can compensate for lack of talent by doubling your efforts, there’s not end to what you can’t do! Paul Rubinov PRR Mar 2006

2. Outline • Answer charge #4 • Answer #3 but not in the way you may have hoped • Answer charge #2 • Address #5 • Answer #6 • Get your advice on #1 Paul Rubinov PRR Mar 2006

3. PRR history (spare) • A brief history of the AFE/TriP • The AFE was designed by John Anderson around the SIFT and SVX ASICs. • John was busy with other designs, so it fell to some of the rest of us to make sure this stuff worked. • See our motto • We got very nervous about making the SVX/SIFT work, especially at 132ns Paul Rubinov PRR Mar 2006

4. PRR history • A brief history of the AFE/TriP • Abder was asked to design a new chip that would work at 132ns • Marvin proposed the basic idea based on lessons learned from SIFT/SVX MCM: • Keep the ASIC as simple as possible: use commercial ADCs, FPGAs, etc. The ASIC would have only what it must: front end Q amp, pipeline and discriminators. • Don’t try to pass fC level signals between different chip. Paul Rubinov PRR Mar 2006

5. PRR history (spare) • Abder designed the Trigger and Pipeline chip by 3/2002! • We worked on designing a replacement MCM for existing boards, so we could avoid making new boards, but it became clear that new boards would be simpler/safer/cheaper • The 1st AFEII TDR is from June 2002 • Dzero lost interest because 132ns went away and John came back and made the AFE work (and GG and JW and MM and others) Paul Rubinov PRR Mar 2006

6. PRR history • We (Juan and Bruce and I) kept pluging away at this because the TriP chip looked very nice in testing. We also had strong support from Marvin. • Our proposal for AFEII was opposed on 2 main grounds. • AFEIs work ok • We needed “crisp” physics case to get support from the collaboration/lab/DOE Paul Rubinov PRR Mar 2006

7. PRR History • Therefore we worked to understand AFE1 problems as best we could. We identified 4 main issues: (D0 note 4500) • SVX saturation – this is a killer but requires very detailed understanding of the detector and MC. Not easy to see at low lumi with the real detector • Tick to tick variation – very easy to see, but not lumi dependent. Paul Rubinov PRR Mar 2006

8. PRR History • We identified 4 main issues (cont.): • Discriminator to analog crosstalk – severe and getting worse. Well demonstrated and understood. • Channel to channel variation – same order as tick to tick variation. Paul Rubinov PRR Mar 2006

9. PRR History • Tick to tick variation – very easy to see, 1pe=10 adc counts Paul Rubinov PRR Mar 2006

10. PRR History • Discriminator to analog crosstalk – severe and getting worse Paul Rubinov PRR Mar 2006

11. AFEII fix by design • “Fix by design” means • Understand the problem • Avoid the situation causing the problem • SVX saturation is caused by resetting the SVX only in the gaps (because reset is slow). Ask Abder to design a chip with a very fast (but gentle) reset. So reset every xing (at 132 ns!) Paul Rubinov PRR Mar 2006

12. AFEII fix by design (cont) • Tick to tick variation is caused by resetting only once per gap. Killed to birds with one stone by resetting every xing! • Discriminator to analog crosstalk. This is caused by discriminators firing while small charges are being integrated by the SVX (we can even tell which discr steps on which analog line by looking at the layout!). We fix this by NOT firing discriminator drivers during the active gate. Paul Rubinov PRR Mar 2006

13. AFEII fix by design (cont) • Channel to channel variation is caused by using only one digital threshold for 64 (128) imperfectly matched analog channels. Our solution is to digitize everything and process every channel individually- every channel has its own pedestal and its own threshold. So analog mismatch can not cause pedestal or threshold mismatch. Paul Rubinov PRR Mar 2006

14. Will the AFEIIt fix the AFE1 problems? Q: Will the AFEIIt address the problems seen on AFE1? A:Yes! By design! • The question is what NEW problems the AFEII has and how we solve them. • Will the AFEII degrade any aspect of current detector performance? Paul Rubinov PRR Mar 2006

15. AFE1 non-problems • AFE1’s are very reliable. • AFE1’s (currently, at 40Mhz) read out with a very low BER. • Both “grey cable” and LVDS links • AFE1’s have a stable calibration for all aspects –cryo, bias, threshold, peds. Paul Rubinov PRR Mar 2006

16. AFEIIt vs AFE1 • Due to shutdown schedule we will not be able to do thorough testing of AFEIIt with beam before going into production. • GG actually pointed this out to director when the shutdown schedule was discussed • Our solution: • Test as much as possible with beam. • Test as much as possible without beam on the platform. • Don’t install a particular flavor of AFEIIt boards in quantity until we know it works. Paul Rubinov PRR Mar 2006

17. AFEIIt vs AFE1 • Strategy to make sure we do no harm: • Get an AFEIIt into CFT stereo slot on platform before shutdown because this requires the least infrastructure and CFT stereo is very well understood. • Instrument CFT stereo first. Leverage that experience to understand CFT axial performance. • Leverage platform experience and the 4CC cryostat to understand PS performance. Bottom line: don’t install boards until sure they are not WORSE than AFE1s they replace. Paul Rubinov PRR Mar 2006

18. AFEIIt vs AFE1 • Strategy to make sure we do no harm: Requires that we be able to operate almost any mixture of AFE1s and AFEIIt’s in the same crate/sequencer, side by side, face to face. • This is what we call “plug compatible” and this was a design requirement. • Same data format as AFE1, but not necessarily the same download. They are very different boards! “Best is the enemy of good” Paul Rubinov PRR Mar 2006

19. AFEIIt vs AFE1 A: We have a solid strategy which we are following to make sure that the AFEIIt will not degrade any aspect of the current detector performance. But this requires that we be able to operate a mixed system of AFEIIt and AFE1 in a transparent fashion.(except for downloads!) Paul Rubinov PRR Mar 2006

20. AFEIIt + AFE1 = ♥ 7 Feb 06 AFEIIt # 6, prototype, inserted into stereo slot 2B0. Data taken: store 4631, runs 215086-215108 (during run 215085 timing was being adjusted). About 7 % of events have readout errors. 17 Feb 06 AFEIIt # 6, with new terminations, inserted into stereo slot 2B0. No readout errors. Data taken: store 4653, runs 215519-215534 (solenoid and toroid off during run 215533) store 4654, runs 215540-215558, SMT Sequencer off store 4658, runs 215596-215600 21 Feb 06 AFEII #12, pre-production, inserted into 2B0 Data taken: store 4664, 36x20 (pbars lost in transfer), runs 215635-215643 Paul Rubinov PRR Mar 2006

21. AFEIIt + AFE1 = ♥ • The 1st run with AFEIIt on platform revealed a readout problem we had not detected before! • No errors bench testing with SaSeq • No errors in Phase V • No errors in CTS with Seq • No errors on platform during calibration or LED injection • Data dependent errors with beam! Paul Rubinov PRR Mar 2006

22. AFEIIt readout errors • Readout errors ~7% in SOME slots on the platform and only with DATA (not even LEDs) • Required a lot of work to understand • But we do understand! • We can cause errors without beam by special “random” firmware • Cross talk in grey cable – can fix by adding series resistors. • But adding series resistors reduces voltage swing very close to the minimum! Paul Rubinov PRR Mar 2006

23. Problem understanding • The “knee” This is AFE 1c! Paul Rubinov PRR Mar 2006

24. Problem understanding • The “cross talk in the middle of VSVX” This is AFEIIt Paul Rubinov PRR Mar 2006

25. Problem understanding • The “cross talk in the middle of VSVX” This is AFE 1c! Paul Rubinov PRR Mar 2006

26. Problem understanding • The “knee” This is #12 in 12B0 Paul Rubinov PRR Mar 2006

27. Problem understanding • The “knee” This is AFE 1c! Paul Rubinov PRR Mar 2006

28. Problem understanding • I think we have an ok model that reproduces the salient features • Problems are caused by: cable, sharing grounds, RC termination Paul Rubinov PRR Mar 2006

29. Problem understanding • The “knee” Paul Rubinov PRR Mar 2006

30. Problem understanding • The “baseline shift” Paul Rubinov PRR Mar 2006

31. Problem fixes • Remove the RC termination on the SEQ! Paul Rubinov PRR Mar 2006

32. Problem fixes • The “baseline shift” is virtually solved Paul Rubinov PRR Mar 2006

33. Problem fixes • The “knee” is much improved Paul Rubinov PRR Mar 2006

34. New idea 12ma -240mV Paul Rubinov PRR Mar 2006

35. Final Fix • Put in the “pull down bias” • Very small layout change • Change from ABT to ACT • Just BOM, no effort, small cost • Gives larger driver (closer to “rails”) • Optimize seq timing • Plug in delay • Reprogram seq to fix cross talk • This allows async running Paul Rubinov PRR Mar 2006

36. Final Fix No errors report in AFEIIt preproduction boards since the “Final Fix” AFEII in 5A0,2,4,6 20 March 06 Pre-production boards inserted in 9A 9A0 1 2 3 4 5 6 7 #12 #14 #18 #20 (afe1 588 543 496 473 484 463 610 477 ) AFEII in 9A0,2,4,6 16 March 06 Pre-production boards inserted in 9A 9A0 1 2 3 4 5 6 7 #12 #14 #18 #20 (afe1 452 527 580 575 542 453 592 485 ) AFEII in 4B0-4B7, 10 March 06 Pre-production boards inserted in 4B0-4B7 4B0 1 2 3 4 5 6 7 #20 #13 #18 #19 #12 #11 #14 #15 (afe1 560 503 612 505 554 511 494 529 ) No readout errors, however 4B2 disabled during tests because of problems with board #18 AFEII in 12B0, 12A4, 11B6, 2A4, 2A0, 12A0 March 2-3 06 Paul Rubinov PRR Mar 2006

37. Readout on the platform • Confident that this is DONE • But took a lot of time Q: What about other aspects of the boards? Will they operate as smoothly, reliably and safely as the current boards? Paul Rubinov PRR Mar 2006

38. Other aspects of AFEIIt • Required for CFT stereo: • Good signal to noise • Downloads/Calibration • Bias • Cryo Paul Rubinov PRR Mar 2006

39. JW@FTG, 2006Mar21 LED Spectra:AFE1 AFEII Paul Rubinov PRR Mar 2006

40. LED Spectra:AFE1 AFEII Paul Rubinov PRR Mar 2006

41. Pedestals, triggering on all crossings AFEII AFE1 Paul Rubinov PRR Mar 2006

42. Pedestals, triggering on clock tick 63 AFE1 AFEII Paul Rubinov PRR Mar 2006

43. LEDs on, rms of pulse height vs VLPC pixel# AFEII #12 in 5A0 AFE1 AFEII Paul Rubinov PRR Mar 2006

44. LEDs on, rms of pulse height distribution vs VLPC pixel # AFEII #14 in 5A2 AFE1 AFEII Paul Rubinov PRR Mar 2006

45. LEDs on, rms of pulse height distribution vs VLPC pixel # AFEII #18 in 5A4 AFE1 AFEII Paul Rubinov PRR Mar 2006

46. LEDs on, rms of pulse height distribution vs VLPC pixel # AFEII #20 in 5A6 AFE1 AFEII Paul Rubinov PRR Mar 2006

47. Peds rms, 5A0,triggering on all crossingsor triggering on clock tick 63 AFEII AFE1 Paul Rubinov PRR Mar 2006

48. Peds rms, 5A2, triggering on all crossingsor triggering on clock tick 63 AFEII AFE1 Paul Rubinov PRR Mar 2006

49. Other aspects of AFEIIt • Required for CFT stereo: • Good signal to noise You bet! And the mapping is correct- same as AFE1 • Downloads/Calibration • Bias • Cryo Paul Rubinov PRR Mar 2006

50. Platform test of AFEIIt • Elog entry 486329 Paul Rubinov PRR Mar 2006