experiment 6 n.
Download
Skip this Video
Download Presentation
Experiment 6

Loading in 2 Seconds...

play fullscreen
1 / 18

Experiment 6 - PowerPoint PPT Presentation


  • 147 Views
  • Uploaded on

Experiment 6. Combinational Building Blocks: Encoders and Decoders. Lab 4 Comments:. The Main Points: Simulation: allowed you to test a circuit before you actually built the circuit Simulator was based on device models

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'Experiment 6' - buzz


Download Now An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
experiment 6

Experiment 6

Combinational Building Blocks: Encoders and Decoders

lab 4 comments
Lab 4 Comments:
  • The Main Points:
    • Simulation:
      • allowed you to test a circuit before you actually built the circuit
      • Simulator was based on device models
      • Device models were used to simulate propagation delays in actual devices
      • Static logic hazards were located, tested (they caused glitches), and removed.
lab 4 comments1
Lab 4 Comments:
  • Procedure Ordering in lab report
  • report should have close to logical flow of what you did in experiment: 1) procedure, 2) results/data, 3) observations… 1) procedure, 2) results/data, observations… etc.
  • Don’t use command style of writing in lab reports
  • Use engineering notation: MHz, kHz, ms, μs, ns (order of magnitudes of 3)
  • Use some horse sense: stand back and verify your results make sense!
lab 5 comments
Lab 5 Comments:
  • The Main Points:
    • The logic analyzer is a test device that is used to view the signal activity of an actual circuit (as opposed to the simulated circuit of Lab 4).
    • The Xilinx Design Methodology was the steps you took to:
      • model a circuit
      • simulate the model
      • implement a circuit (on the CPLD) with the same output characteristics of the model
    • Implementing circuits on the CPLD was much easier than wiring the circuit using discrete logic gates (previous experiments).
lab 5 comments1
Lab 5 Comments:
  • Title and annotate timing diagrams (and all diagrams for that matter)
  • Don’t allow your VHDL code to wrap: examine your outputs before you submit them
  • Put a title banner on all your VHDL files
  • Put some comments into your VHDL code
  • Print your VHDL code from Xilinx environment and include with your report (don’t put code into body of report)
  • Print timing simulations from ModelSim and include with your report: don’t cut and paste
instructional objectives
Instructional Objectives:
  • To learn concurrent statement in VHDL.
  • To design combinational building blocks in VHDL and to implement them on the CoolRunner II CPLD.
instructional objectives1
Instructional Objectives:
  • To learn concurrent statement in VHDL.
  • To design combinational building blocks in VHDL and to implement them on the CoolRunner II CPLD.
vhdl basics
VHDL Basics
  • ENTITY– black box description of circuit that declares inputs and outputs, their type, and their size
  • ARCHITECTURE – what’s inside the box…. Specifies the implementation of your circuit
vhdl entity
VHDL Entity

ENTITY modulename IS

PORT ( input1 : IN STD_LOGIC;

input2 : IN STD_LOGIC;

output1 : OUT STD_LOGIC_VECTOR(0 TO 7);

output2 : OUT STD_LOGIC);

END modulename;

vhdl architecture
VHDL Architecture

ARCHITECTURE myarch OF modulename IS

internal signal declarations;

BEGIN

concurrent statement1;

concurrent statement2;

concurrent statement3;

END myarch;

concurrent statements signal assignment
Concurrent Statements:Signal Assignment (<=)

ARCHITECTURE my_arch OF module_name IS

SIGNAL internal_sig : STD_LOGIC;

BEGIN

-- a comment begins with two hyphens

internal_sig <= input1 AND input2;

output1 <= “10101010”;

output2 <= internal_sig XOR output1(3);

END my_arch;

concurrent statements conditional signal assigment
Concurrent Statements:Conditional Signal Assigment

ARCHITECTURE myarch OF modulename IS

BEGIN

output2 <= b WHEN (sel = “01”) ELSE

c WHEN (sel = “10”) ELSE

d WHEN (sel = “11”) ELSE

a; -- default

END myarch;

concurrent statements selected signal assignment
Concurrent Statements:Selected Signal Assignment

ARCHITECTURE myarch OF modulename IS

BEGIN

WITH sel SELECT

output2 <= b WHEN “01”,

c WHEN “10”,

d WHEN “11”,

a WHEN OTHERS;

END myarch;

xcrplus development board
XCRPlus Development Board

Xilinx

CoolRunner

CPLD

64 macrocells

xcrplus development board1
XCRPlus Development Board

a

f

b

g

  • Active high
  • Common cathode connected to GND via a transistor

e

c

d

7-Segment

LED Displays

cat1

experiment 6 overview
Experiment 6 Overview

P1: Design and implement a Binary-Coded-Decimal

(BCD) to 7-segment Display Decoder

P2: Design and implement an 8:3 Priority Encoder

P3: Integrate the circuit from the two previous steps and use the BCD-7seg Decoder to display your output

slide18

7-Seg Decoder

Priority Encoder

B3

B2 AA-AG

B1 CATH

B0

I7

I6

I5 Y2

I4 Y1

I3 Y0

I2

I1 STROBE

I0

Connect

to ground

4 switches

(sensors)

Alarm Control

Break-in Armed

OFF/ON_L Alarm

Key Comparator

I3 EQ

I2

I1

I0

4 switches

(access code)

Digital Alarm System