RE: [W. Arden/A.Allan Email (3/16)]: Gartner/Dataquest article and your comments.

1. 2004 ITRS ORTC Overview Alan Allan/Intel Corp Stresa, Italy, 04/19,20/04 IRC/ITWG Workshop PreparationDRAM, MPU, Flash Model Foils[Update of IRC 04/08/04, Rev2 Review]

2. RE: [W. Arden/A.Allan Email (3/16)]: Gartner/Dataquest article and your comments. Gartner/Dataquest makes the following key points/questions in the article [bracket comments are A. Allan’s]: - Does the [leading-edge company roadmap to published ITRS] gap have potential to bifurcate [separate] the industry? - Will these disparities [internal company versus public roadmap] actually create a significant technology gap [multiple technology paths/timing which suppliers must support with limited R&D resources]? - Does the apparent gap reflect a marketing spin to make the rest of the world believe a given company is keeping pace with [or pulling ahead of] the industry? [These points will be important to discuss in the Stresa IRC meetings to communicate status for the 2004 industry update and also to prepare for the 2005 Roadmap technology node frameworks for DRAM, MPU/ASIC/SOC, and Flash product technology trends. Sony/Toshiba "theoretical roadmap" presented at the last (3/9) European IRC Teleconference, and similar conclusions were discussed that the current technology and roadmap claims of leading-edge companies will be tested in the marketplace by "construction analysis" companies such as Chipworks and Silicon Strategies. Documenting the actual production of 90nm technology claims by leading edge manufacturers and their future roadmaps for DRAM, MPU/ASIC/SOC, and Flash will be crucial to documenting the 2004 status and to prepare us for the 2005 Roadmap work. It was also mentioned in the IRC Telecons that it will be necessary to do cross-TWG work between FEP and PIDs and Design to develop ITRS/ORTC consensus models for the Flash product (and also any other embedded fabrics for the Design TWG System Integration Chapter SOC model). Per 4/8 IRC, Need: Data on actual devices 90nm DRAM, MPU, Flash, SOC/ASIC]

3. Fig 2 Production Ramp-up Model and Technology Node 100M 200K Development Production 10M 20K 1M 2K Alpha Tool Beta Tool Production Tool Volume (Parts/Month) 100K Volume (Wafers/Month) 200 First Two Companies Reaching Production 10K 20 First Conf. Papers 1K 2 0 12 24 -24 -12 Months Source: 2003 ITRS - Exec. Summary Fig 2

4. Technology Nodes: Back to 3-year cycle Year of Production 2002 [Actual] 2003 2004 2006 2007 2009 2010 2012 2013 2015 2016 2018 hp90 hp65 hp45 hp32 hp22 hp130 Technology Node (nm) 2-Year Technology Cycle [1998-2002actual] 3-Year Technology Cycle Source: 2003 ITRS - Exec. Summary Table C Near Term Long Term

5. 3-year Node-Cycle 2-year Node-Cycle 3-year Node-Cycle [DRAM] Company A Company B Company C [DRAM Half-Pitch] 03 04 2020 Source: STRJ, ITRS PIDS ITWG Survey, ca. 2Q03 ITRS 2003: 2003/100(-110nm?) - 2019/16nm: Average 0.5x/2.5years

6. 1.4u 1986 1989 1992 1995 1998 2000 2004 2002 2007 2010 2013 2016 2019 1983 1.0u .72u Sub– Micron Tech nology Era Began! [= 0.5^(1/6) = 0.8909/year] .51u .36u .32u [0.5^(1/4) = 0.8409/year =] .29u .25u 3-year Node-Cycle 3-year Node-Cycle 2-year Node-Cycle .23u .21u .18u .15u [0.5^(1/6) = 0.8909/year =] .13u .11u .10u 90n Nano– technology Era Begins! 65n 45n 32n 97 98 03 04 22n 16n Gate-Length Nano–technology Era Began - 1999! 2020 Source: STRJ, ITRS PIDS ITWG Survey, ca. 2Q03 ITRS 2003: 2003/100(-110nm?) - 2019/16nm: Average 0.5x/6years

7. Fig 4 Definition of the Half Pitch. [DRAM half-pitch determines the 2003 ITRS “node”] DRAM ½ Pitch = DRAM Metal Pitch/2 MPU/ASIC Poly Silicon ½ Pitch = MPU/ASIC Poly Pitch/2 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 • Metal 1 (M1) • Pitch • Poly • Pitch • Metal • Pitch Typical DRAM Metal Bit Line Typical MPU/ASIC Un-contacted Poly Typical MPU/ASIC Contacted Metal 1 Source: 2003 ITRS - Exec. Summary Fig 4

8. Cell Pitch Poly Pitch Proposal: NAND Flash feature size = fflash = Poly Pitch Still need: “Design Factor” (Aflash) And Cell Array Efficiency (CAEflash) And Bits/Chip Model To calculate Cell Size = Af2 And Chip Size = (Af2 x N) / CAE Figure XX Proposed minimum feature size for NAND Flash Memory Source: FEP ITWG

9. Proposal: NAND Flash feature size = fflash = M1 or Poly Pitch Still need: “Design Factor” (Aflash) And Cell Array Efficiency (CAEflash) And Bits/Chip Model To calculate Cell Size = Af2 And Chip Size = (Af2 x N) / CAE M1 Pitch Poly Pitch Cell Pitch Figure XX Proposed minimum feature size for NOR Flash Memory Source: FEP ITWG

10. 2001-2002-2003-2004 ITRS NO CHANGES [Except Add Logic Metal 1 (M1) consistent w/Interconnect] ; However: 2003/’04 Press Announcements:ACTUAL Logic M1 and Flash Poly HP =65nm in Production in 2005-06New “Node” HP DRIVERS? 1000 M1 Half Pitch [Actual, also same as 2001 ITRS Interconnect TWG “Local Interconnect”] 2001 MPU Printed Gate Length 2001 MPU Physical Gate Length Technology Node - DRAM Half-Pitch (nm) 100 2001 DRAM ½ Pitch = 2yr cycle Thru 2004; then = DRAM HP 2001 MPU/ASIC ½ Pitch (Poly) “Average” Logic “Node” Logic M1 HP 2001 ITRS DRAM HP/ Node Leading Edge Logic Roadmaps “Node” plus Associated 2003 ITRS Printed GL and Final Physical GL = Plus Gartner/Dataquest “Bifurcation” = 2-year 3-year Cycle Cycle 10 Logic prGL 1995 1998 2001 2004 2007 2010 2013 2016 Flash Model Poly HP Node Proposal = ongoing 2yr cycle= Year of Production Logic “Node” (1x) plus Associated 2003 ITRS Printed GL (.7x) and final Physical GL (.5x) = Source: 2001 ITRS - Exec. Summary, ORTC

11. 2003 ITRS Renewal ORTC Table Header/”Targets”: 2003 ITRS Technology Node Header (**Unchanged from 2001/2002 ITRS):Near-Term Long Term Notes ---------------------------------- -------------------------------- ----- 2003 2004 2005 2006 2007 2008 2009 2010 2012 2013 2015 2016 2018 hp90 hp65 hp45 hp32 hp22 DRAM Unchanged 100 90 80 70 65 57* 50* 45 35* 32 25* 2218* Other ORTC Tracked Technology Trends (optional - use by TWG Tables as needed): Poly Unchanged 107 90 80 70 65 57* 50* 45 35* 32 25* 2218* NEW Logic M1: 120 107 95 85 76 67 60 54 48 42 38 34 30 27 24 21 UNCHANGED: MPU Pr GL: 65 53 45 40 35 32* 28* 25 22 20* 18 16 15* 13 11 10* MPU Ph GL: 45 37 32 28 25 22* 20* 18 16 14* 13 11 10* 9 8 7* Logic “Node”: 92 80 70 62 55 50 44 40 35 31 28 25 22 20 18 16 * Not visible in 2001 ITRS due to no annual columns between "Near Term" and "Long Term" column ranges. The 2001 ITRS Long Term columns are retained for continuity of technology nodes. ** DRAM Half-Pitch Nodes unchanged, however cell design factor improvement has been significantly delayed in the 2003 ITRS. Node timing is based on original 2001 ITRS glossary definition of 10Ku/mo manufacturing with Production-Capable Equipment and Materials. ***Note: Logic Half-Pitch (HP) was based on Un-contacted Logic Poly HP in 2001 ITRS. In the 2003 ITRS, Logic “Metal 1” (M1) was added and correlated with IC TWG “Local Wiring” Pitch/2 [120nm/2003, plus a 3-year target cycle trend]. “Logic Node” = (M1+PrGL)/2 ** ***

12. 2003 ITRS Renewal ORTC Table Header/”Targets” (w/ Logic “Node”): • 2003 ITRS Technology Node Header (Unchanged from 2001/2002 ITRS):Near-Term Long Term Notes ---------------------------------- -------------------------------- ----- • 2003 2004 2005 2006 2007 2008 2009 2010 2012 2013 2015 2016 2018 hp90hp65 hp45 hp32hp22 • DRAM Unchanged 100 90 80 70 65 57 50 45 35 32 25 2218 • Other ORTC Tracked Technology Trends (optional - use by TWG Tables as needed): • NEW Logic M1: 120 107 95 85 76 67 60 54 42 38 30 27 21 • MPU Pr GL: 65 53 45 40 35 32 28 25 20 18 15 13 10 • Logic “Node”: 92 80 70 62 55 50 44 40 31 28 22 20 16 • **** Note: • - Logic “Node”= [(Logic half-pitch (M1) + Logic Printed Gate Length prGL)/2]; • NOT definition of Technology Node used by the ITRS • However helps explain the Logic public Roadmap and “Node” announcements which differ in half pitch from DRAM Node. ****

13. Fig 7 Flash Poly HP Model Proposal [Same as 2003 ITRS Poly HP thru 90nm/’04; then 2-yr cycle] Source: 2003 ITRS - Exec. Summary Fig 7

14. Fig 7 Note: ACTUAL DRAM HP Node Production Timing – 1 Year Delay* (2-year Node Cycle) Flash Poly HP Model Proposal [Same as 2003 ITRS Poly HP thru 90nm/’04; then 2-yr cycle] Source: 2003 ITRS - Exec. Summary Fig 7 * Per PIDS Survey

15. Fig 8 Source: 2003 ITRS - Exec. Summary Fig 8

16. (Cell Array Area / Chip Size) x 100 = Cell Array Efficiency (%): Chip Size = (A x f 2 x Nbits)/CAE Cell Array Area = Cell Area x number of bits (2 n) f 2 f 2 Flash Example: Cell Area = 2.5x4 x f 2 = 10 f 2 Cell Area = Cell Area Factor (A) x f 2 ; f = technology node (half-pitch) feature size; Example: Cell Area = 2x4 x f 2 = 8 f 2 Chip Size Model Calculation Illustration – DRAM(& Flash)

18. Model 180nm Flash 1G “Intro”? Model 90nm Flash 4G “Intro”? Model 45nm Flash 16G “Intro”? 180nm Flash .5G “Pilot”? 90nm Flash 2G “Pilot”? 65nm Flash 8G “Pilot”? 45nm Flash 32G “Pilot”? 180nm 0.25G Production? 90nm 1G Production? 65nm 4G Production? 22nm 16G Production? Flash = 10 x f2 Flash = 10 x f2 Flash = 10 x f2 Flash = 10 x f2 Flash Model Node?: 360 255 180 128 90? 65? 45? 32? 22? [2-year Node cycle?] STM Samsung Flash Cell Size?: 0.32 0.16 .080 .040 .020 .010 0.005

19. Flash Technology/Market Example: STM – 90nm, 0.08um2 Cell; 130nm/0.16um2 Cell ST | STMicroelectronics Announces First 90nm NOR Flash Technology ...... Built in 90nm technology, ST's latest NOR Flash memory cells occupy a silicon areaof only 0.08µm2[=> 9.88f2], a 50% size reduction from the current 130nm generation [0.16um2]...us.st.com/stonline/press/news/year2003/t1325h.htm …. "The 50% reduction in memory cell size afforded by the new technology corresponds to a 40% reduction in die size for 128Mbit devices and even more for larger memories, which significantly reduces the cost per bit." [Analysis (64Mb): Implies 90nm 64Mb (2^26): 67.11e6x0.08u2x1e-6 mm2/u2 = 5.37mm2/.47(est. CAE) =11.4mm2? => 64Mb@130nm = 11.4/.6 = 19.0mm2] [Analysis (128Mb): Implies 90nm 128Mb 2^27): 134.2e6x0.08u2x1e-6 mm2/u2 =10.74mm2/.47(est. CAE) =22.8mm2? => 128Mb@130nm = 22.8/.6 = 38.1mm2]

20. Flash Technology/Market Example: E.News – Samsung 2G Pilot Production Model: [2003 Flash: 2Gb Pilot = 2^31 = 2.148e9 x 0.08u2(90nm STM cell size, 10f2) = 171.8mm2/.72(DRAM Intro CAE) = 238mm2; 1Gb Production? = 85.9mm2/.63(DRAM CAE) = 136mm2] Samsung Produces 90nm NAND Device Online staff -- Electronic News, 9/16/2002 Samsung Electronics Co. Ltd. today said it has taken the lead in the 90-nanometer process race, claiming to be the first to production with its piloted 2Gbit NAND flash memory device. The process technology will be used in Samsung's coming 300mm fabrication plant -- line 12, opening in Q3 2003 -- and is slated for 512Mbit and 1Gbit DRAM production[ITRS:1G/100nm]. In addition, today's news marks a strategy shift for Samsung, dubbed "The New Memory Growth Theory." The theory predicts memory technology will face a new order, particularly in consumer segments, that doubles density every 12 months [1-year node cycle? Or 2x multi-cell?]. Based on that, Samsung plans to move further away from the PC realm and is exploring markets with higher memory demand, such as mobile devices. "Demand for memory is expanding beyond the traditional PC platform to next-generation mobile devices, gaming products, digital TV and networking systems, which require higher performance memory," said Chang Gyu Hwang, president of Samsung Electronics Memory Division, in a statement. "As a result, Samsung is devoting more resources to develop memory solutions that boost system functionality in tomorrow's communication devices and digital appliances." According to Samsung, DDR SDRAMs, RDRAMs and graphics DRAMs make up 70 percent of its DRAM sales, with 35 percent of memory sales generated from mobile and digital appliance markets. With the new strategy in place, Samsung is forecasting $14 billion in memory revenue in 2005 and $25 billion in memory revenue by 2010.

21. Flash Technology/Market Example: Si.Strategies – Samsung 50nm/.025u2 cell 4G Development Process: Samsung makes 70nm 4Gb flash, 80nm 512Mb DRAM SS 09/29/03 http://www.siliconstrategies.com/article/showArticle.jhtml?articleId=15200632 Samsung advances processes for 4-Gbit flash, 512-Mbit DRAM By Peter Clarke Silicon Strategies 09/29/2003, 6:54 AM ET.. ..SEOUL, South Korea -- Korean electronics giant Samsung Electronics Company Limited said Monday (September 29, 2003) that it has developed a 4-Gbit NAND-style flash memory and 512-Mbit DRAM in advanced manufacturing process technologies. However, the company did not say what memory interface the memories comply with, or when they would be mass produced. The NAND-flash was fabricated it in a 70-nanometer process technology and the DRAM was made using an 80-nm process, Samsung said. In addition Samsung announced something called Fusion memory, which includes the monolithic integration of memory with logic. The 4-Gbit NAND flash memory has a memory cell size of 0.025 square microns and includes a 30-nm thick metal gate of tungsten, which reduces inter-cell resistance and noise level. The new tungsten gate to be adaptable to designs at 50-nm [=> 10f2?] processing node, Samsung said. Samsung said it expects the chip to help it maintain its 65 percent share of the NAND flash market. The company is targeting 70 percent annual growth in NAND flash sales from $1.1 billion in 2002... Model: [2005? Flash: 8Gb Development = 2^33 = 8.590e9 x 0.02u2(45nm? cell size, 10f2) = 171.8mm2/.72(DRAM Intro CAE) = 238mm2; 1Gb Production? = 85.9mm2/.63(DRAM CAE) = 136mm2]

22. MPU Chip size (mm2) – Historical Trends vs Unchanged 2001-03 ITRS Model* 1000 800mm2 Litho Field Size 286mm2 2 per Field Size New: 704mm2 Litho Field Size 572mm2 Litho Field Size HP MPU 310mm2 “130nm” 193mm2 ?MB ?Ghz CP MPU 140mm2 100 “90nm” 114mm2 ?MB ?Ghz CP Shrink 70mm2 *1999 Leading-Edge .18u CP MPU: 512KB (28Mt [58.3%] x 1.18u2/t = 34mm2) + 20Mt Logic x 5.19u2/t = 104mm2 + 2mm2 OH= 106mm2 = Total 48Mt x ave 2.92u2/t = 140mm2 *1999 Leading- Edge .18u HP MPU: 2MB (113Mt [81.9%] x 1.18u2/t = 135mm2) + 25Mt Logic x 5.19u2/t = 130mm2 + 45mm2 OH= 310mm2 = Total 138Mt x ave 2.25u2/t = 310mm2 * ITRS Design TWG MPU Transistors/Chip Model: ~2x/Node = 2x/2yrs from 1999 - 2001; then 2x/3yrs from 2001- 2016 10 1980 1985 1990 1995 2000 2005 2010 2015 2020 “90nm” 100Mt 1MB 4Ghz ?mm2

23. Fig 3 Technology Node Compared to Actual Wafer Production Capacity Technology Node Distribution 10 W.P.C.= Total Worldwide Wafer Production Capacity(Relative Value *) Source: SICAS** W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C * Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2003.  The area of each of the production capacity bars corresponds to the relative share of the Total MOS IC production start silicon area for that range of the feature size (y-axis). Data is based upon capacity if fully utilized. hp720nm >0.7mm hp510nm 1 0.7-0.4mm hp360nm Feature Size (Half Pitch) (mm) Feature Size of Technology <0.4mm <0.4mm 0.4-0.3mm <0.3mm <0.3mm <0.2mm 25% <0.2mm hp255nm 25% <0.16mm 0.1 25 %? SIA/SICAS Data: 1-yr delay from ITRS Timing to 25% of MOS IC Capacity 0.3- 0.2mm 25% 25% hp180nm ITRS Technology Node 0.2- 0.16mm hp180 Actual hp130 Actual hp350 Actual hp250 Actual hp90 hp65 hp127nm 3-Yr 3-Yr 2-Yr 0.01 <0.16mm 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 <0.11um F’cast Source: 2003 ITRS - Exec. Summary Fig 3 Year hp90nm ** Source: Semiconductor Industry Capacity Statistics (SICAS) – collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of July, 2003

24. CSTNSG CD Control Survey Feedback 1)  Messages from  7 usable (logic only) respondents seem consistent with first survey in 2003 (which had only 3 respondents in 2003). 2)  None are meeting the 10% CD Control targets at present.   Only one is within 1% of meeting the Goal. 3)  Majority support the 25/75 Litho/FEP  variance (sigma squared) allocation. 4)  Relaxing the nominal Printed Gate Length targets  does not  solve  the red cell Etch and Litho problem - need consensus on relaxation of gate length control from 10% to 12% in order to change cell colors from red. 5)   Respondents are evenly split regarding relaxation of the 10% target; and objectors cite their company designers as reason for inflexibility. 6)  Need to identify and survey inputs from a specialized subset of transistor/process modelers/designers who are responsible for communicating between the manufacturing process engineers and the designers - to confirm short term "yellow/cross-hatched design workarounds“ - to identify long-range pre-competitive potential solutions which can be addressed by the industry academic and commercial Research and Development resources.  (drive currents, gate delays, voltage levels, etc.)  - to constitute new focus research topics for "Design for Manufacturability and Design for Manufacturing Variability Tolerance."    - Model recommendations must also include interactions/tradeoffs with other variables (oxide thickness targets, doping targets, etc.). 7)  Need to get specific commitments from SRC, Consortia, Government Labs, etc. to commit priority, spending, and personnel resources to address the CD Control "Red Brick Wall" challenges. 8)  Need public domain Modeling and Simulation R&D that sheds light on variability issues by describing of future transistor design options (including vertical, ie tri-gate, emerging transistor options. (AR:  PIDS/Design cross-TWG partnership). [Additional comments:  long-term:  Non-classical CMOS solutions also may have problems; short range:  manufacturing methods sharing solutions; analyze problem and solicit work-around description proposals from design community.]  Per 4/8 IRC, Need: More product related details, especially regarding yield dependencies by specific product.

25. NEMI PEG/ITRS System Driver Integration • ITRS System Driver Overview presented to PEG Chairs in Anaheim • PEG Emulator Tables under review supplied by ITRS Design TWG Co-Chairs Juan-Antonio Carballo/IBM Austin and Andrew Kahng/UC San Diego • Analyzing for development of connection between the PEG tables and the leading-edge technology System Drivers of the ITRS • Initial assessment: the key to the connection of the two roadmap drivers will be coordination with NEMI PEG Chairs to capture historical and forecast trend data and to model the migration of end market applications semiconductor device “product fabrics” • In order to model the continuous transition from “System-in-Box” => “System-on-Board” => “System-on-daughter-board” => “System-in-Package” => “System-on-Chip”  • Potential focus topics: 1) “Design for Manufacturability/Test”; 2) Cost-reduction; 3) Performance/Power Management Tradeoffs; and 4) Technology Integration: a) wireless; b) optoelectronic; and c) novel/emerging devices 

26. NEMI PEG/ITRS System Driver Integration (cont.) ITRS “Emulator” Reference Models: • DRAM (Office) (ORTC) • MPU (Office) (ORTC) • Hi-Performance ASIC (Various) (ORTC) • PDA (Consumer/Low Power) (Design System Drivers) New System Driver Embedded “Fabrics”

27. Backup

28. Fig 7 Note: ACTUAL DRAM HP Node Production Timing – 1 Year Delay* (2-year Node Cycle) 1.5-year Node Cycle ca 2003 Sony/Toshiba Playstation Chip per Semiconductor Insights Jan’03 At 1.5yr node cycle (0.7937x/yr), a model of  the theoretical Toshiba roadmap looks like: Year         1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 H-pitch     328   260   206   164   130   103   82     65      ??     ??     ?? Phys. GL  176    140   111    88    70      56    44     35      ??     ??     ?? Source: 2003 ITRS - Exec. Summary Fig 7 * Per PIDS Survey

29. Fig 8 ca 2003 Sony/Toshiba Playstation Chip per Semiconductor Insights Jan’03 1.5-year Node Cycle At 1.5yr node cycle (0.7937x/yr), a model of  the theoretical Toshiba roadmap looks like: Year         1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 H-pitch     328   260   206   164   130   103   82     65      ??     ??     ?? Phys. GL  176    140   111    88    70      56   44     35      ??     ??     ?? Source: 2003 ITRS - Exec. Summary Fig 8

30. Toshiba T300 Family Summary Technical Specification Summary • Product Name TC300 Process CMOS4 90nm (gate length: 70nm) low-k dielectric process • Metal Wire11 layers of copper metal interconnect • Internal Power Supply Voltage1.2V ± 0.1V • Input/Output Voltage 2.5V, 3.3V, or 1.8V (optional) • Gate Density 400,000 gates/mm2 or more • Gate DelayVery high speed type: 9.5 picoseconds(ps)High speed type: 11psLow-power type: 14ps (fanout = 1, CIV x 4 cells) • Power Consumption7nW/MHz/Gate (CIV x 1 cell) • DRAM Core4-32 megabits per block at 64/128/256 bits wideTypically two to four cores per design • SD Type DRAM Clock Cycle: 300MHz maximumData Transfer Rate: 9.6GB/sec.I/O Width: 256 bits maximumBit Scale: 4-32Mb/Block • FA Type DRAM Random Access Time: 6-8nsI/O Width: 288 bits maximumBit Scale: 4-9Mb/Block Source: http://www.toshiba.com/taec/press/to-274.shtml

31. Sony Toshiba Press Release • (See Text in Notes View)

32. Actual Scaling Acceleration, Or Equivalent Scaling InnovationNeeded to maintain historical trend DRAM MPU

33. Goal: Increase Speed by 2x Speed/2-2.5 years Actual Scaling Acceleration, Or Equivalent Scaling InnovationNeeded to maintain historical trend MPU Clock Frequency Historical Trend: Gate Scaling, Transistor Design contributed ~ 17-19%/year Architectural Design innovation contributed additional ~ 21-13%/year “90nm” 100Mt 1MB 4Ghz

34. Table C Table C Rounded Node Targets versus Actual [Calculated] Trend Numbers [including historical actual production ramp update: 2000/180; 2002/130] Source: 2003 ITRS - Exec. Summary Table C

35. 2003 ITRS “Rounded” vs “Calculated *” Comparison: 2003 ITRS Renewal Technology Node Header (Rounded, UNCHANGED from 2001/2002 ITRS) plus Historical and Calculated: 2003 ITRS 2003 ITRS Historical (u) (3-yr) Historical** (nm) (2-yr) Near-Term (3-yr) Long Term (3-yr) ------------------------------- ----------------------------- ----------------------- ------------------------ 1986 1989 1992 1995 1998 2000 2002 2004 2007 2010 2013 2016 hp90 hp65 hp45 hp32 hp22 DRAM HP (Rounded): 1.00 0.70 0.50 0.35 250 180 130 90 65 45 32 22 DRAM HP (Calculated:) 1.02 0.72 0.51 0.36 255 180 127 90.0 63.6 45.0 31.8 22.5 ** Recent History Technology Node Production Ramp Updated by Japan PIDS and IRC members at July San FranciscoITRS Meetings: ~ 1yr delay from 2001 ITRS * Calculated from trend formulas: [= 0.5^(1/2T) = 0.5^(1/4) = 0.8909/year] = -10.9% CAGR/yr; for T=2yrs [= 0.5^(1/2T) = 0.5^(1/6) = 0.8409/year] = -15.9%CAGR/yr; for T=3yrs [New Slide]

36. Fig 3 Technology Node Compared to Actual Wafer Production Capacity Technology Node Distribution 10 W.P.C.= Total Worldwide Wafer Production Capacity(Relative Value *) Sources:SICAS** W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C * Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2003.  The area of each of the production capacity bars corresponds to the relative share of the Total MOS IC production start silicon area for that range of the feature size (y-axis). Data is based upon capacity if fully utilized. >0.7mm 1 0.7-0.4mm Feature Size (Half Pitch) (mm) Feature Size of Technology <0.4mm <0.4mm 0.4-0.3mm <0.3mm <0.3mm <0.2mm <0.2mm <0.16mm 0.1 0.3- 0.2mm ITRS Technology Node 0.2- 0.16mm 0.01 <0.16mm 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 Year ** Source: Semiconductor Industry Capacity Statistics (SICAS) – collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of July, 2003 Source: 2003 ITRS - Exec. Summary Fig 3

37. 1984 LEM: 0.5Bcm2 LEL: .07Bcm2 OLE: 1.6Bcm2 TLE: 2.2Bcm2 OIC: 4.6Bcm2 TIC: 6.8Bcm2 OSC: 1.3Bcm2 Total: 8.1Bcm2 1992 LEM: 1.1Bcm2 LEL: .25Bcm2 OLE: 2.7Bcm2 TLE: 4.2Bcm2 OIC: 4.3Bcm2 TIC: 8.5Bcm2 OSC: 2.1Bcm2 Total: 10.6Bcm2 1996 LEM: 3.2Bcm2 LEL: .74Bcm2 OLE: 5.3Bcm2 TLE: 9.2Bcm2 OIC: 6.3Bcm2 TIC: 15.5Bcm2 OSC: 4.0Bcm2 Total: 19.5Bcm2 2000 LEM: 3.7Bcm2 LEL: 1.5 Bcm2 OLE: 7.7Bcm2 TLE: 12.9Bcm2 OIC: 7.0Bcm2 TIC: 19.9cm2 OSC: 5.0Bcm2 Total: 24.9Bcm2 2005 LEM: 7.2Bcm2 LEL: 2.5Bcm2 OLE: 8.9Bcm2 TLE: 18.6Bcm2 OIC: 9.0Bcm2 TIC: 27.6Bcm2 OSC: 5.3Bcm2 Total: 32.9Bcm2 Technology Node vs Actual Wafer Production Capacity * Total LE (TLE) % of Total IC Capacity: 1984: 32.4% ; 1996: 59.4% ; 2005: 67.4% 1992: 49.4% 2000: 64.8% • IEM Total LE (TLE) # Equiv. 20Kwspm “Fabs” (if all capacity in each size): • 19841992199620002005 • 5/6” (133mm): 65.7 125 275 385 556 • 8” (200mm): 29.2 55.7 122 171 247 • 12” (300mm): 13.0 24.8 54.3 76.0 110 2003 IEM Node: 2003 IEM 4Q03: IEM 2Q03: <.88-[0.72um]-.60 = N-5 1988-1989-1990 <.60-[0.51um]-.44 = N-4 1991-1992-1993 SICAS > 0.7u <.44-[0.36um]-.30 = N-3 1994-1995-2000 SICAS > 0.4u <.30-[0.25um]-.22 = N-2 1997-1998-1999 SICAS > 0.3u <.22-[0.18um]-.15 = N-1 1999-2000-2001 SICAS < 0.3u <.15–[0.13um]-.11 = N 2001-2002-2003 SICAS < 0.2u <.11- 0.090um-.075 = N+1 2003-2004-2005 SICAS < 0.16u <.075-0.063um-.053 = N+2 2006-2007-2008 <.053-0.045um-.038 = N+3 2009-2010-2011 <.038-0.032um-.026 = N+4 2012-2013-2014 <.026-0.022um-.019 = N+5 2015-2016-2017 <.019-0.016um-.013 = N+6 2018-2019-2020 IC: 22.8 x .928 = 21.2Bcm2 IC: 23.5 x .859 = 20.2Bcm2 >=N-5=19% N + N-1 = 38% N-2=11% N-3=18% N-4=14% >=N-5=23% N-1=27% N-2=13% N-3=23% N-4=14% 49% SICAS Capacity Snapshot ca. 2002: >=N-5=19% N-4=14% N-2=9% N-3=16% N-1=18% N=24% 127nm 180nm255nm360nm510nm>600nm ?% + ?% * Note: SICAS data is % of Total Available MOS IC Industry Capacity (if fully utilized - does not include Bipolar, Discrete, or Optoelectronic Capacity) 4Q02: = 38% 11% 18% 14% 19% 4Q01: 28% 20% 16% 16% 20% 4Q00: 38% 19% 19% 24% 4Q99: 29% 19% 21% 31% N (<127nm) = ~??% (Year 2002) N (<127nm) = ~0% (Year 2000) 48% Yano Capacity Snapshot ca. 2000: SICAS Capacity Snapshot ca. 2Q03: 127nm 180nm255nm360nm510nm>600nm 4Q00?: 0% 27% 13% 23% 14% 23% 127nm 180nm255nm360nm510nm>600nm 2Q03: 24% 18% 9% 16% 14% 19% 40% 42% Work in Progress – Do Not Publish

38. Note: The 2003 ITRS returns to 3-year node cycle at 90nm, which will begin Production Ramp in 2004. Semico estimates 3 years until 23% of Wafer demand [IC’s Only? Units or Area?] and 90nm + 130nm to be 38% of demand. Add 11% 65nm demand and 48% of demand will be consumed at the leading edge. And the remaining six trailing nodes capacity must share 51% at 3%-12% each. [1986] [2007] [ITRS Intro Year] [1989] [1992] [2004] [1995] [8%] [1997] [2001] [1999] [pluss AA ITRS, SICAS Analysis] Work in Progress – Do Not Publish Semico 2007 Node Capacity Split Estimate, ca Nov’03

39. ITRS 2001 “Moores Law” Targets: DRAM: 2x/2.5yrs; 1.05x/yr Chip Size MPU: 2x/node = 2x/3years; FLAT Chip Size Density Trends (bits/cm2, t/cm2) – ITRS / ORTC

40. MPU Clock Frequency Actual vs ITRS Historical <- > 1999 ITRS 2001 ITRS 100,000 2X / 4 Years 10,000 Actual Scaling Acceleration, Or Equivalent Scaling InnovationNeeded to maintain historical trend 1,000 Frequency (MHz) 2X / 2½ Years 100 MPU Clock Frequency Historical Trend: Gate Scaling, Transistor Design contributed ~ 17-19%/year Architectural Design innovation contributed additional ~ 21-13%/year 2X / 2 - 2½ Years 10 1 1980 1985 1990 1995 2000 2005 2010 2015 Sources: Sematech, 2001 ITRS ORTC

41. 90nm Announcements [Source: GoogleTM11/23/03 search: “90nm”] • EBN - ASIC industry moves to 90nmMonday, November 24, 2003. ASIC industry moves to 90nm. Market leadersIBM Microelectronics, Fujitsu unveil new processes. www.ebnonline.com/story/OEG20020607S0064 - 33k - Nov 24, 2003 • IBM and Xilinx prepare for production of first 90nm chips on ...IBM Microelectronics Press Release: IBM and Xilinx preparefor production of first 90nm chips on 300mm wafers. ... www-3.ibm.com/chips/news/2002/1216_xilinx.html • CHARTERED, VIRAGE LOGIC EXPAND EFFORTS FOR 90NM CHIP DESIGN... CHARTERED, VIRAGE LOGIC EXPAND EFFORTS FOR 90NM CHIP DESIGN Virage Logic joins Chartered'sNanoAccess Alliance, provides Technology-Optimized Semiconductor IP ...www.charteredsemi.com/media/corp/ 2003n/20030918_Vlogic.asp • Embedded News - Synopsys Develops Silicon Libraries for ...... Synopsys Develops Silicon Libraries for Chartered's 90nm Process. ... The two companieshave also begun validation of a joint 90nm reference design flow. ...www.embeddedstar.com/press/content/ 2003/9/embedded10547.html • Techweb > News > No Sub-90nm "Show Stoppers," Panelists Say > No ...... No Sub-90nm "Show Stoppers," Panelists Say November 12, 2003 (11:12am EST) By Michael Santarini, EEdesign San Jose, Calif. - For ...www.techweb.com/wire/story/TWB20031112S0002 - 40k - Nov 24, 2003 • Applied Materials Pushes the Sub-90nm Agenda... Infrastructure News July 15, 2003 Applied Materials Pushes the Sub-90nmAgenda By Michael Singer. SAN FRANCISCO -- Looking to improve ...news.earthweb.com/infra/article.php/2235421 - 54k - Nov 24, 2003 • CHARTERED AND MOSYS COLLABORATE ON 90NM HIGH DENSITY MEMORY ...... CHARTERED AND MOSYS COLLABORATE ON 90NM HIGH DENSITY MEMORY COMPONENTS MoSys joins chartered's NanoAccess Alliance; Silicon validation of 1T-SRAM by Q1 2004. ...www.charteredsemi.com/media/corp/ 2003n/20030918_mosys.asp • ST | STMicroelectronics Announces First 90nm NOR Flash Technology ...... Built in 90nm technology, ST's latest NOR Flash memory cells occupy a silicon areaof only 0.08µm2, a 50% size reduction from the current 130nm generation. ...us.st.com/stonline/press/news/year2003/t1325h.htm • Intel Corporation - Feature Articles about Intel Research and ...... Intel's integration of silicon germanium, 90nm process technology, includingthe latest strained silicon advances, and proven 300-millimeter wafer ...www.intel.com/labs/features/si09022.htm

42. 90nm Announcements [Source: GoogleTM11/23/03 search: “90nm”] (cont.) • Topan Chunghwa to make 90nm semiconductor masks... General-purpose ICs. Topan Chunghwa to make 90nm semiconductor masks. ... Ltdwill commence production of 90nm semiconductor masks this year. • Fujitsu to release 90nm process ASIC... Fujitsu to release 90nm process ASIC. Wednesday, September 10, 2003.Fujitsu plans to bring 90nm structured ASIC to market in 2004. ...www.simmtester.com/page/news/ shownews.asp?title=Fujitsu+to+release+90nm+process+ASIC&num=6101 • PRESS RELEASE / NECエレクトロニクス株式会社、90nm...Press Release 2003年9月9日. NECエレクトロニクス株式会社、90nmセルベースLSI設計にシノプシスのStar-RCXTを採用 ...www.synopsys.co.jp/pressrelease/2003/20030908.html - 13k - Nov 24, 2003 • IBM and Intel draw up 90nm battle plans... [Advert]. IBM and Intel draw up 90nm battle plans Strained silicon takes onSOI. ... Instead it claims it has the fastest drive currents on 90nm silicon. ...www.theinquirer.net/?article=6681 • TechOnLine - Texas Instruments Sees Its 90nm Process Performance ...10-14-03. Texas Instruments Sees Its 90nm Process Performance Exceeding EarlierGeneration By Over 50 Percent - R&D Innovations Deliver Impressive Gains. ...www.techonline.com/community/news/29665 • 90nm ( Ldrawn=70nm ) CMOS ASIC TC300 FamilyFile Format: PDF/Adobe AcrobatPage 1. 90nm ( Ldrawn=70nm ) CMOS ASIC TC300 Family 2003 http://www.semicon.toshiba.co.jp/engPRODUCT GUIDE BCE0012A 2003-2 Page 2. ...www.semicon.toshiba.co.jp/eng/ prd/asic/pdf/bce0012a.pdf • Electrospec alpha wire, belden wire, mil spec wire, m22759 wire, ...... fujitsu to make transmeta processor on 90nm Wednesday, October 08, 2003. ... volume productionof efficeon on a 90nm process is slated for the second half of 2004. ...www.electrospec-inc.com/news/news_article.asp?ID=1265 • Mentor Graphics Delivers Comprehensive Design Support for Xilinx ...Mentor Graphics Delivers Comprehensive Design Supportfor Xilinx 90nm Spartan-3 Platform FPGAs. ...www.mentor.com/press_releases/apr03/1046984875029.html • Altera to ship FPGAs made with 90nm process... Altera to ship FPGAs made with 90nm process. Tuesday, September 16,2003 ... Ltd. is slated to release its 90nm process into production. ...www.simmtester.com/page/news/shownews.asp?num=6119

43. 90nm Announcements [Source: GoogleTM11/23/03 search: “90nm”] (cont.) • UMC begins production of 90nm-based ICs... UMC begins production of 90nm-based ICs. ... (UMC) has started pilot productionof customer ICs based on its recently developed 90nm logic process. ...www.hardwares.globalsources.com/am/article_id/9000000039241/ page/showarticle?action=GetArticle • Getting to 90nm and Beyond: Multisite Design Collaboration and ...Home > Company > Events > Webinars > Getting to 90nm and Beyond: Multisite DesignCollaboration and Management Solutions in Cadence Custom IC Design. ...www.cadence.com/webinars/ webinars.aspx?xml=gettingto90nm • Embedded News - World's First 90nm Programmable Chips Made by ...Books, Music, Movies. World's First 90nm Programmable Chips Made byXilinx. 4/1/2003 - Xilinx, Inc. (NASDAQ: XLNX), the industry leader ...www.embeddedstar.com/press/content/ 2003/4/embedded7935.html • STMicroelectronics - ASIC Solutions - 90nm CMOS090 Design ...90nm CMOS090 Design Platform, Process, libraries and design platformfor System-on-Chip and ASIC solutions The new CMOS090 design ...us.st.com/stonline/prodpres/dedicate/ soc/asic/90plat.htm • The Tech Report - Intel produces its first 90nm chips... Intel produces its first 90nm chips by Andrew Champion - 09:40 am, September3, 2003 Rumors about Intel's Prescott chip may be swirling ...www.tech-report.com/onearticle.x/5604 • Forbes.com: Sony says 90nm PS2 chip production to start in Oct... Related quotes IBM, 91.70, + 0.52. 10/7/03 4:02:00 PM ET. Sony says 90nm PS2chip production to start in Oct Reuters, 10.07.03, 11:54 PM ET ADVERTISEMENT. ...www.forbes.com/newswire/2003/10/07/rtr1102426.html • TOSHIBA TELLS ADVANCED SOC STRATEGY, LAUNCHES 90NM TC300 FAMILY ...... Email Us Your Technical Questions. TOSHIBA TELLS ADVANCED SOC STRATEGY,LAUNCHES 90NM TC300 FAMILY TARGETED AT HIGH-PERFORMANCE APPLICATIONS. ...www.toshiba.com/taec/press/to-274.shtml • A novel self-aligned shallow trench isolation cell for 90nm 4Gbit ...File Format: PDF/Adobe Acrobat - View as HTMLA novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND Flash EEPROMs Masayuki Ichige, Yuji Takeuchi, Kikuko Sugimae, Atsuhiro Sato, Michiharu ...www.vlsisymposium.org/technology/tec_pdf/T7Bp1.pdf • Taiwan Moves Towards 90nm Process Technology... NEA Readers: Enter an article ID. for quick access. ->help, Taiwan MovesTowards 90nm Process Technology. ... This year, 90nm R&D is being done. ...www.asiabiztech.com/wcs/frm/ nea/200206/manu_190776.html

44. 5) Toshiba [TAEC] Takes 90nm Process LeadOnline staff -- Electronic News, 1/13/2003 • Toshiba Corp. • “…disclosed details of its [TC300] 90nm process… • … first to reach volume production at such an advanced technology node… • …begun sampling… • …begin mass production in Q2[03], with high-volume production beginning in Q3... • …ahead of the likes of Intel, IBM and TSMC… • …expected to reach production at 90nm in the second half of 2003… • …11 layers of copper wire and low-k insulating material… • …100 percent increase in gate integration… • [400Kgates/mm2 => 200Kgates/mm2 for “130nm” TC280… • …20 percent increase in gate speed… • …50 percent reduction in power consumption… • …compared to the previous generation 0.13-micron process technology (TC280)… • …0.13-micron SOCs have been in production since October 2001… • …Richard Tobias, VP… ASIC and foundry business unit at TAEC… • … aluminum interconnect version into production first and following with a copper interconnect version afterward… • …two types of embedded DRAM optimized for speed or density. "Toshiba is currently the only company with 90nm embedded DRAM suitable for mass production," Tobias added… • … developed a new, advanced EDA methodology for TC300… • …sign-off interface uses the industry-standard Synopsys static timing analysis and standard test interface language… • …supported by full-chip hierarchical design implementation and verification methodologies… • …added enhanced signal integrity and cross talk analysis tools…” [1.5-yr Roadmap] 90nm Announcements (cont.) – Toshiba TC300

45. Flash Technology/Market Example: EET/ISuppi – NAND/NOR Share Analysis http://www.eetimes.com/semi/news/OEG20040210S0027 Flash market to leap in 2004 By Peter Clarke Silicon Strategies February 10, 2004 (2:16 p.m. ET) LONDON — The market for flash memory is predicted to reach $15.70 billion in 2004, up 39 percent from its 2003 total of $11.32 billion, according to Betsy Van Hees, a principal analyst with market research company iSuppli. The estimate include flash revenues from multichip packages. Following even stronger growth in 2003, which was up 43.5 percent, 2004 growth will again be driven by a buoyant market for NAND devices, Van Hees said. NAND flash was responsible for $3.83 billion of the total in 2003, while NOR flash accounted for $7.48 billion. In 2004 the NAND market is expected to grow by 63.9 percent while NOR is expected to grow 25.8 percent. Market totals are estimated at $6.28 billion and $9.42 billion respectively. NAND is expected to overtake NOR flash in 2007, when the markets are expected to be worth $11.57 billion and $11.04 billion respectively. The NAND market's strength knocked Intel, a traditional NOR flash supplier, from the top spot to No. 4 in the 2003 rankings in 2003. It was replaced atop the list by Samsung. No. 1 Samsung Semiconductor had estimated revenues of $2.2 billion and an overall flash market share of 19.5 percent. Spansion, the flash memory joint venture between Advanced Micro Devices Inc. and Fujitsu Ltd., was the No. 2 flash supplier with a 16.3 percent market share on estimated revenues of $1.84 billion. Toshiba ranked third with a 16.1 percent market share and estimated revenues of $1.82 billion. Intel trailed with 15 percent market share on revenue of $1.69 billion, a decline of 18 percent from 2002. "Intel was flat by units in 2003. But I think we could see Intel pointing its Strata-flash multi-level technology at NAND sockets," said Van Hees.

46. Flash Technology/Market Example: IDG News – Toshiba 65nm http://www.infoworld.com/article/03/12/10/hnsonytosh_1.html Toshiba, Sony close to 65nm sample productionNew process technology vital for Sony's planned consumer electronics processorBy Martyn Williams, IDG News ServiceDecember 10, 2003  TOKYO - Toshiba Corp. and Sony Corp. are close to beginning trial production of semiconductor chips using a manufacturing process more advanced than any in commercial use today, they said Thursday. ..The technology is capable of making chips with features as small as 65 nanometers and its development is vital for Sony to produce its planned Cell microprocessor. The chip, which it is developing with Toshiba and IBM Corp., is expected to form the heart of its future PlayStation 3 games… …Toshiba's trial production of sample chips using the 65-nanometer technology will begin in March 2004, said Junichi Nagaki, a spokesman for Toshiba in Tokyo…. .. Construction is scheduled to end in January 2004 and initial production on a 90-nanometer process is to begin in the middle of 2004 after which it will be upgraded to handle the 65-nanometer process. The plant will process 300-millimeter diameter wafers…