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# Lecture 10: Circuit Families

Lecture 10: Circuit Families. Outline. Pseudo-nMOS Logic (Ratioed Logic) Dynamic Logic Pass Transistor Logic. Introduction. What makes a circuit fast? I = C dV/dt -&gt; t pd  (C/I) D V low capacitance high current small swing Logical effort is proportional to C/I

## Lecture 10: Circuit Families

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### Presentation Transcript

1. Lecture 10: Circuit Families

2. Outline • Pseudo-nMOS Logic (Ratioed Logic) • Dynamic Logic • Pass Transistor Logic 10: Circuit Families

3. Introduction • What makes a circuit fast? • I = C dV/dt -> tpd (C/I) DV • low capacitance • high current • small swing • Logical effort is proportional to C/I • pMOS are the enemy! • High capacitance for a given current • Can we take the pMOS capacitance off the input? • Various circuit families try to do this… 10: Circuit Families

4. Ratioed Logic

5. Ratioed Logic

7. Pseudo-nMOS • In the old days, nMOS processes had no pMOS • Instead, use pull-up transistor that is always ON • In CMOS, use a pMOS that is always ON • Ratio issue • Make pMOS about ¼ effective strength of pulldown network 10: Circuit Families

8. Pseudo-nMOS 10: Circuit Families

9. Pseudo-NMOS VTC 10: Circuit Families

10. Pseudo-nMOS Design 10: Circuit Families

11. Pseudo-nMOS Gates • Design for unit current on output to compare with unit inverter. • pMOS fights nMOS • Iout = 4I/3 – I/3 10: Circuit Families

12. Pseudo-nMOS Gates • Design for unit current on output to compare with unit inverter. • pMOS fights nMOS 10: Circuit Families

13. Pseudo-nMOS Design • Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H • G = 1 * 8/9 = 8/9 • F = GBH = 8H/9 • P = 1 + (4+8k)/9 = (8k+13)/9 • N = 2 • D = NF1/N + P = 10: Circuit Families

14. Pseudo-nMOS Power • Pseudo-nMOS draws power whenever Y = 0 • Called static power P = IDDVDD • A few mA / gate * 1M gates would be a problem • Explains why nMOS went extinct • Use pseudo-nMOS sparingly for wide NORs • Turn off pMOS when not in use 10: Circuit Families

15. Ratio Example • The chip contains a 32 word x 48 bit ROM • Uses pseudo-nMOS decoder and bitline pullups • On average, one wordline and 24 bitlines are high • Find static power drawn by the ROM • Ion-p = 36 mA, VDD = 1.0 V • Solution: 10: Circuit Families

16. Pseudo-NMOS Design • Pseudo-nMOS gates will not operate correctly if VOL>VIL of the driven gate. • This is most likely in the SF corner. • Conservative design requires extra weak pMOS. • Another choice is to use replica biasing. • Idea comes from analog design. • Replica biasing allows 1/3 the current ratio rather than the conservative ¼ ratio of earlier. 10: Circuit Families

17. Replica Biasing 10: Circuit Families

18. Ganged CMOS 10: Circuit Families

19. Ganged CMOS 10: Circuit Families

21. Improved Loads 10: Circuit Families

22. Improved Loads (2) Differential Cascode Voltage Switch Logic (DCVSL)

23. DCVSL Example

24. DCVSL Example

25. DCVSL Transient Response 10: Circuit Families

26. Pass-Transistor Logic

27. Example: AND Gate 10: Circuit Families

28. NMOS-Only Logic 10: Circuit Families

29. NMOS-Only Switch

30. NMOS Only Logic: Level Restoring Transistor • Advantage: Full Swing • Restorer adds capacitance, takes away pull down current at X • Ratio problem

31. Restorer Sizing 10: Circuit Families

32. LEAP • LEAn integration with Pass transistors • Get rid of pMOS transistors • Use weak pMOS feedback to pull fully high • Ratio constraint 10: Circuit Families

33. Complementary Pass Transistor Logic

34. CPL • Complementary Pass-transistor Logic • Dual-rail form of pass transistor logic • Avoids need for ratioed feedback • Optional cross-coupling for rail-to-rail swing 10: Circuit Families

35. Alternative CPL 10: Circuit Families

36. Transmission Gate 10: Circuit Families

37. Resistance of Transmission Gate

38. Pass Transistor Circuits • Use pass transistors like switches to do logic • Inputs drive diffusion terminals as well as gates • CMOS + Transmission Gates: • 2-input multiplexer • Gates should be restoring 10: Circuit Families

39. S S Pass-Transistor Based Multiplexer S VDD GND In2 In1 S

40. Transmission Gate XOR 10: Circuit Families

41. Delay in Transmission Gate Networks 10: Circuit Families

42. Delay Optimization

43. Transmission Gate Full Adder Similar delays for sum and carry

44. Other Pass Transistor Families • DPTL (Differential Pass Transistor Logic) • DPL (Double Pass Transistor Logic) • EEPL (Energy Economized Pass Transistor Logic) • PPL (Push-Pull Pass Transistor Logic) • SRPL (Swing Restored Pass Transistor Logic) • DCVSPG (Differential Cascode Voltage Switch with Pass Gate Logic) 10: Circuit Families

45. Pass Transistor Summary • Researchers investigated pass transistor logic for general purpose applications in the 1990’s • Benefits over static CMOS were small or negative • No longer generally used • However, pass transistors still have a niche in special circuits such as memories where they offer small size and the threshold drops can be managed 10: Circuit Families

46. Single Clock 2-Phase System T/2 T 3T/2 10: Circuit Families

47. Shift Register 10: Circuit Families

48. Shift Register • When f = 1, data move through the first transmission gate to the inverter. 10: Circuit Families

49. Charge Leakage 10: Circuit Families

50. Charge Leakage 10: Circuit Families

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