Architectural Characterization of an IBM RS6000 S80 Server Running TPC-W Workloads

1. Architectural Characterization of an IBM RS6000 S80 Server Running TPC-W Workloads Lei Yang & Shiliang Hu Computer Sciences Department, University of Wisconsin - Madison

2. Outline • TPC-W Benchmarks in Java • IBM RS6000 S80 Enterprise Server • Hardware Counters in S80 • Experiment Results • Problems and Future work • Conclusions

3. TPC-W benchmark • TPC-W is the TPC Council’s newest benchmark for Transactional Web Environments (E-Commerce) Modeling an online book store similar to www.amazon.com • Browsing 95% browsing, 5% transactions • Shopping 80% browsing, 20% transactions • Ordering 50% browsing, 50% transactions • Transactional Web Environments: • Web serving of static and dynamic content • Online Transaction processing (OLTP) • Some decision support (DSS)

4. IBM RS6000 S80 Enterprise Server • 6 RS64-III Pulsar processors (451MHz) • 4-issue in-order Super Scalar microprocessor with on chip 128KB L1 I-Cache, 128KB L1 D-Cache and 8MB L2 Cache. • No Branch Prediction, Aggressive early branch resolution • Coarse grain 2-context Multithreading. • SMP system. Snooping bus inter-processor connection. • 8GB main memory, Huge disk volumes. And very high bandwidth IO systems.

5. System Configuration: SUN Java Web Server2.0 Java Servlet http JDBC DB2 DBMS Processes Emulated Java Servlet Browser Java Virtual Machine Java Virtual Machine Performance Monitor Performance Monitor Performance Monitor Kernel Extension AIX kernel RS64-III processor RS64-III processor 32bits Control word 32bits Control word Snooping bus

6. Hardware Counters in S80 • 3 levels of objects can be counted with their own counting contexts: - System level counting, whole system level context - Process / Process group, process level context - Individual thread, thread level context. • 3 major components - 8 Built-in hardware counters in each RS64-III processor. - Kernel extension to AIX 4.3 - Performance Monitor API in the next release of AIX. • Some Problems with current version of PM API. - Cannot count for individual processor. - Some Listed events are not available.

7. Hardware Counters in S80: Countable Events • Processor events - execution cycles and the number of instructions executed. • Instruction mix events - Pipeline M, S, B and S instructions executed. • Branch events - Conditional branch T/NT events, unconditional branches, zero cycle branches. • Address Translation events - TLB/SLB and ERAT/IERAT miss and duration events. • Cache events - Cache misses and latencies for each of the L1 I-Cache L1 D-Cache L2 Cache • Bus and multi-processor bus snooping events - bus utilization. multi-processor bus snooping events

8. Results: CPI for RBE, Java Web Server and DB2

9. Results: CPU Cycle Counts Cycle Counts

10. Results: Instruction Dispatch • Browsing Mix Dispatch Percentage % Dispatch Percentage %

11. Results: Instruction Dispatch • Shopping Mix Dispatch Percentage %

12. Results: Instruction Dispatch • Ordering Mix Dispatch Percentage %

13. Results: Instruction Mix • Browsing Mix Instruction type Percentage %

14. Results: Instruction Mix • Shopping Mix Instruction type Percentage %

15. Results: Instruction Mix • Ordering Mix Instruction type Percentage %

16. Results: Branch Behavior Browsing Mix Shopping Mix • Branches unconditional • Branches conditional not taken • Zero cycle branch not taken • Zero cycle branch taken • Branches conditional taken • Branch to link register taken • Branch to counter taken • Absolute branches

17. Results: Branch Behavior Ordering Mix • Branches conditional taken • Branch to link register taken • Branch to counter taken • Absolute branches • Branches unconditional • Branches conditional not taken • Zero cycle branch not taken • Zero cycle branch taken

18. Results: Cache Behavior Browsing Mix Shopping Mix Latency/cycles • L1 I cache miss duration latency • L1 D cache miss duration latency

19. Results: Cache Behavior Shopping Mix Ordering Mix Latency/cycles • L1 I cache miss duration latency • L1 D cache miss duration latency

20. Results: Cache Behavior Browsing Mix Shopping Mix Ordering Mix Count • L2 miss count per instruction • L1 I cache miss count per instruction • L1 D cache miss count per instruction

21. Problems & Future Works • Problems: - Large Dataset - Network and Server end software are the bottleneck? - Hardware counters vs. Simulations. • Future works: - Measurement of other transactional processing and web serving benchmarks for comparison. -More architectural characterizations such as multithreaded processors, multiprocessor scaling and multiprocessor snooping bus issues.

22. Conclusions • Server end Software is critical for high-end servers - Network and Server end software are the bottleneck - This is true both for high end commercial server systems and other high performance parallel computers designed for scientific or engineering computing. • Preliminary performance characterization shows: - CPU utilization is highly dependent upon the application workloads. - High dispatching mechanism on RS64III appears less efficiently used. - Branch instructions are second to load and store instructions. - L2 cache miss rate is unreasonably low and L1 D-cache miss latency is considerable larger than that of L1 I-cache.

23. Acknowledgement • Trey Cain for setting up Java TPC-W and discussion • Morris Marden for helping quiet the machine and discussion • Prof. Mikko Lipasti for guidance and support • Everyone helped us