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  1. 矽奈米元件電物理特性及量測 Heng-Sheng Huang 主講:黃恆盛 教授 國立台北科技大學機電整合所 Nov. 28, 2001

  2. Contents • Nano device revolution - silicon age? or other materials ? • Silicon nanodevice physical limits - ELJ effect,MSJZ effect,SDE tunneling effect. • Nano silicon device measurement - the C-R method • Conclusions

  3. Silicon Age or Other Materials?

  4. 奈米電子世紀何時來? 半導體的故事

  5. Semiconductor Road Map (nm) 1015 1014 1013 1012 1011 1010 109 108 107 106 105 DRAM 1.4 Times/Year Transistor Number per chip 64GB (2015) Neuron Number in Brain Gate Length Increasing Technology difficulty year

  6. Scaled-Down Device Characteristics Source: IEEE Spectrum, July 1999

  7. Scaled-Down Device Characteristics Source: IEEE Spectrum, July 1999

  8. Scaled-Down Device Characteristics Year Gate Length Gate Oxide Thickness Gate Leakage Current Threshold Voltage Power Supply 2000 – 2006 0.13mm – 0.10mm ~20Å ~0.05nA/mm2 (1/20 of off current) 0.3V 1V 2020 0.018mm <10Å 0.05mA/mm2 (50 times of off current) <0.1V ≦0.6V

  9. CMOS Revolution IG ~ mA – Gate dielectric materials (low tunneling leakage) VT ~ 0.2V – Control gate materials (фms optimization),channel engineering VDD ~ 0.6V – high k dielectric materials BJT-like CMOS?

  10. RTD Single Electronics RTD Vertical Gate Structure RTD Nanotubes Bulk CMOS SOI Molecular Switch 2040 Today 2020 TECHNOLOGY IN THE INTERNET ERAFuture Scaling Beyond Bulk CMOS

  11. 100b Number of transistors on a chip 10b in thousands 100-billion transistors Moore’s law prediction 1b processors 100,000 1-billion transistors 10,000 Pentium III Xeon 1,000 80386 80286 Pentium III 80486 100 Pentium II 4004 8086 Pentium Pro 10 Pentium 8080 1 '70 '75 '80 '85 '90 '95 '00 '05 '10 '15 ‘20 ‘25 ‘30 CPU with Multimedia Capability Road Map

  12. Integration Revolution — A Monster 2020 0.018mm Ultimate Generation? 2020 – 2040 or 2050 Integration Continues. 2015 64GB DRAM 1-Billion-Tx CPU 2025 1TB DRAM VDD=0.6V, VT=0.1V 100-Billion-Tx CPU IG ~ mA 2050 32TB DRAM VDD<0.6V, VT=0.1V 4-Trillion-Tx CPU IG ~ mA

  13. Is it possible to design a 100-Million-Transistor Chip in 100 Days A/MS=analog/mixed signal ASIC = application-specific IC CPU = central processing unit PLD = programmable logic device I/O pads CPU core Memory DSP core RAM ROM I/O pads I/O pads Control CPU DSP PLD DSP book RAM ROM A/MS A/MS ASIC ROM RAM I/O pads Board components Virtual components SOURCE: MENTOR GRAPHICS CORP.

  14. Centralized Computing Personal Computing Network-Centric Computing Mainframe/Minicomputer Internet/Intranet Information Network Host-based Network Client-Server Network WAN/ Data Comm. Computer LAN Digital TV Computer Computer IN SPC MPEG-II Computer Comm. Consumer Electronics Comm. Consumer Electronics Comm. Consumer Electronics Comm. Consumer Electronics Video phone/ conferencing Analog-based/ Broadcast TV, VCR, ... Telephone with S/W (Switch) Very little Multimedia Digital Convergence heading to CATV We are here Digital Revolution Technology Convergence

  15. Internet Services & Networking Personal IA ( Mobile Phone: Smart/Super) ISP/ASP NSP Protocols: & Middle ware Networking (Access Security & Traffic) Home IA (A/V) RTOS SoC (CPU + DSP + RF + Embedded Memory + …) Mobile IP RTOS WAP Enterprise (Thin Clients: WBT, …) Services / SW Development Applications Development IA 產業組成圖

  16. Nano device physical limits ELJ effect (Extension Lateral Junction Effect)

  17. Inconstant Unit Channel Conductance Model (Inconstant Channel Oxide Thickness Model) Ids~μeffCox (Leff )W/Leff(Vg-Vth) Vds (ELJ effect)

  18. ELJ Effect The Relationships among Various Length Definitions Lmet =Li+Lj,dep Leff =Li+Lj,dep+Lacc =Lmet+Lacc ≒Lmet( ifθ’≒1) Lacc =Ldj,acc+Lsj,acc≒2(Lj-Lovlap) =2Lovlap[(1/ θ’)-1]

  19. The Channel Resistance Rchannel =Ri,MOS + Ri,dep + Racc =[(Li/Qi )+( Lj,dep /Qj, eff )+( Lacc /Qacc,eff )]/µeffW = Leff[(α/Qi )+( β/Qj, eff )+( γ /Qacc,eff )]/µeffW = Leff /µeff Qi, eff W =Vds / Ids ~ Leff / Qi, eff W (4.1) Here, α(Leff)+ β(Leff) + γ(Leff) = 1,and Qj, eff = Lj,dep (Qi,sj Qi,dj )/( Qi,dj Lsj,dep + Qi,sj Ldj,dep(Vds)) (4.2) Qacc, eff = Lacc (Qd,accQs,acc )/(Qd,acc Lsj,acc + Qs,acc Ldj,acc(Vds)) (4.3) Qi, eff(Leff) = 1/ [(α/Qi )+( β/Qj, eff )+( γ /Qacc,eff )] = (Vg-Vt) Cox,eff (Leff)= (Vg-Vt) εox /dox,eff(Leff) As Vds is small,µeff≒constant for devices without halo implant

  20. The Channel Resistance For advanced MOS devices(γ≒0 as θ’≒1 and Vds is small) Qi, eff(Leff)≒1/ [(α/Qi )+( β/Qj, eff )] ≒ (Vg-Vt) Cox,eff (Leff) ≒ (Vg-Vt) εox /dox,eff(Leff) For a long channel device(α>>β) Qi, eff(Leff) ≈ 1/[(α/Qi)+(β/Qj, eff)]≒Qi(constant) = (Vg-Vt)Cox(constant)=(Vg-Vt)εox /dox(constant) Rchannel = Leff / µeff Qi,eff W ~ Leff / W  For a short channel device α β Qi,eff(Leff) andCox,eff (Leff) dox,eff(Leff) PS: Qi =CoxV Cox=εox/dox The unit channel conductance G = μCox

  21. The Relationship between Cox,eff (or dox,eff ) and Leff

  22. The Inconstant Channel Conductance Model The Relationship between Cox,eff(or dox,eff ) and Vds Rchannel(Vds)=Leff(Vds)/WµeffQi,eff(Vds) ~Leff(Vds)/Qi,eff(Vds) ~ 1/Qi,eff(Vds ) Leff is nearly Vds independent (or weak dependent) Therefore, as Vds Qi,eff(Vds) Rchannel dox,eff Cox,eff

  23. The Effective Channel Conductance Model The Relationship between Cox,eff(or dox,eff ) and Vgs Vgs ELJ Effect dox,eff Cox,eff

  24. The Inconstant Channel Conductance Model The Effective Current Unit Factor G=μC Without halo region   G(Leff)=μoCox,eff(Leff) With halo region G(Leff)=μhalo (Leff)Cox,eff(Leff)

  25. The Mobility function , μhalo(Leff) , for NMOS PS:the degradation of mobility due to special process step becomes measurable

  26. The channel mobility difference between N/PMOS No halo Region existing(without spike annealing process) PS:this technology is more important for nano device applications Mobility degradation due to halo impurity

  27. Nano device physical limits MSJZ(MOS-Surface Junction transistor –Zener)Effect

  28. The surface channel can be partitioned to three regions surface concentration of carriers

  29. The MSJZ Model For Nano Mos Devices 1.The MOS/Surface-Junction-transistor/surface-Zener-diode (“MSJZ”) model is set up and adopted “surface current equation”. 2.A novel MSJZ model that is used to describe the entire channel current behaviors, considering the 2-D effect. 3.Current density and continuity equations: Ids = Ids(y) = Idrift(y) + Idiffusion(y) + IR-G(y)(A/um) 4.The surface channel be partitioned to three regions: drift region, diffusion region and R-G region. (or MOS region, SJT region and surface-zener region)

  30. Load line analysis before Ids saturation

  31. Load line analysis after Ids saturation

  32. Nano device physical limits — SDE(Source /Drain Extension)tunneling leakage

  33. The electron leakage paths of an off state NMOS device The whole leakage paths in an NMOS device when operated in off state. This condition likes the NMOS transistor of an inverter circuit at Vin=VLOW. The leakage paths include SDE direct tunneling leak、junction leak and channel leak (Note: Ichannel and Ijunction are too small that can be neglected).

  34. The concerned gate direct leakage components in an inverter circuit when operated in both “Logic-High” and “Logic-Low”. (Here channel leak Ichannel and junction leak Ijunction are neglected in this situation.) 

  35. The various leakage components Is/Id/Isub of an NMOS device operand which can be determined as the voltage is biased at gate to source/drain/substrate.

  36. The practical measured I-V curves of IS/D and Isub tunneling leak in (a) NMOS and (b) PMOS. The device size is W/L=50/0.5(μm) and gate oxide thickness, dox=2.3nm. (a) NMOS (b) PMOS

  37. The measured SDE tunneling leakage current increases with a longer Lov length in both n and p-MOS. PS:Lov is determined using C-R method (a) NMOS (b) PMOS

  38. The gate direct tunneling leakage currents of gate to SDE overlap region and to substrate. (a) NMOS (b) PMOS

  39. The measured SDE tunneling leakage current increases with a higher SDE impurity concentration in both n and p-MOS. (a) NMOS (b) PMOS

  40. A set of various gate direct leakage currents in an inverter circuit operated in both Vin=Vhigh and Vin=Vlow. dox=23nm

  41. (a) (b) (a)The variation of the JS/D leakage current density of NMOS in an inverter when operated at Vin=Vhighwith different gate oxide thickness. (b)As the same condition of PMOS when operated at Vin=Vlow.

  42. Nano silicon device measurement The C-R method

  43. The Relationship of various length Leff = Lmask - ΔL ΔL = 2Lovlap + Lpb Leff is the effective channel length Lpb is the length of process bias Lmet is the metallurgical channel length

  44. Extraction of Leff • I-V method • S&R(Shift and Ratio) Method • C-V method • Decoupled C-V Method • C-R Method • Capacitance Ratio Method

  45. The Comparison of C-R and S&R Method I-V method:Ids~μeffCoxW/Leff(Vg-Vth) VdsLeff △L C-R method: without 2D effect & Rsd effect 2D effect Rsd effect Lpb,Lovlap △L Leff (Here‚Lovlap Lpb Leffall are useful parameters)

  46. S&R Method Ids0= µeffCoxW(Vg-Vtho)Vds/Leff0 ~Vds/Rchannel0 Idsi = µeffCoxW(Vg-Vthi)Vds/Leffi ~Vds/Rchanneli S0(Vg)= dRchanne0/dVg =Leff0 df(Vg-Vth0)/dVg Si(Vg)= dRchannei/dVg =Leffi df(Vg-Vthi)/dVg f(Vg-Vth0)=1/(µeffCoxW(Vg-Vth0)) f(Vg-Vthi)=1/(µeffCoxW(Vg-Vthi))

  47. S&R Method r(δ,Vg) = S0(Vg)/Si(Vg- δ) Source: IEEE Spectrum, 2000

  48. S&R Method PS:The extracted △L result is not constant -function of (L^ mask) Source: IEEE Spectrum, 2000

  49. Decoupled C-V Method Cgc = CoxWLcap Ctot = Cgc+2Cov= CoxWLcap +2Cov(F) Cgc is the intrinsic gate-to-channel capacitance Lcap is the capacitively defined channel length Source: IEEE Spectrum, 1994

  50. C-R Method(High Frequency Measurement Structure) 以NMOS為例 Source: JJAP 2001