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MURI Plans

This document outlines the MURI plans for device modeling and characterization focused on strained silicon (Si) and germanium (Ge) transistors. It details the collaboration with industry leaders like SRC, AMD, IBM, and TSMC. The primary objective is to enhance performance through modeling/calibration of single event transients (SET) in state-of-the-art strained Si and forward-looking strained devices. Strategies include analyzing stress effects, tuning band structure, and employing advanced materials for improved charge transport and mobility enhancement. Future steps involve the application of first-principles methods to refine models.

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MURI Plans

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  1. MURI Plans S. E. Thompson March 27, 2005

  2. OUTLINE • SRC and AMD, AMAT, IBM, Intel, TSMC, TI, UMC funded device modeling/characterization work • Plans: Single event transient • Start with SRC strained Si modeling/calibration • SET on State-of-the-art uniaxial strained Si (90-45nm) • SET on Future strained devices • Strained Ge transistor • Strained Si and Ge on (110) wafers

  3. Many Ways to Do Strain stress stress 45nm Si1-xGex Si1-xGex Intel 2004 EDL TI 2004 VLSI AMAT 2004 IEDM IBM 2005 VLSI TSMC/Freescalse 2005 Samsung 2005 VLSI Nitride a-Si a-Si Gate Gate Hoyt Removable film pre-anneal 1-2.5GPa stress film Even more on high stress layers Post salicide

  4. Strain Being Adopted by All Strained Si Source: Ti Fujitsu 45 nm CompressiveNitride TensileNitride Si1-xGex Si1-xGex Gate Gate stress stress p-type MOSFET STI PMOS NMOS Source Chipworks: 90 nm Intel,IBM,AMD,TI,Fujitsu

  5. Why Strain: Very Impressive Performance 2004 IEDM Intel

  6. Significantly Alters Band Structure/Transport Biaxial Tension Uniaxial Longitudinal Compression Heavy Hole E K <110> Uniaxial Longitudinal Tension Light Hole Valance Band warping, changes m*, m

  7. Stress Contours 45 nm 140 nm 30 nm -536 120 nm Si0.83Ge0.17 Si0.83Ge0.17 (μm) -83 403 95 STI STI 31 (μm) MPa Source FLOOPs

  8. Device Level Calibration: SRC/Intel Funded • Industrial samples • 30 nm to 1um Si trasistors from 3 companies • Unstressed, uniaxial and biaxial stressed wafer • Bulk and SOI • Fully depleted SOI /Metal Gate • High k/metal gate and sub-micron Ge channel devices

  9. Four-Point Bending Set-Up Force Force Z Y X Strain Force Strain Force Z Y X Bending device

  10. Strain Enhanced Mobility: Model / Measured 50 SiGe S/D [4] Data Uniaxial Longitudinal 40 Model 30 20 Biaxial 500 10 300 Mobility Enhancement (%) -300 -500 0 Biaxial Rim -10 Uniaxial Transverse -20 -30 -40 -50 Stress / MPa

  11. 6 Band K P Including Confinement Schrodinger’s Equation and Poisson’s Equation solved self-consistently using the Finite-Difference Method.

  12. Si and Ge Band Structure Si Ge HH LH HH LH No Stress Top Bottom Top Bottom Biaxial Stress Longitudinal compression

  13. In and Out-of-Plane Masses (Ge) Uniaxial Stress Biaxial Stress m|| m| m| m|| kz kz ky ky kx kx

  14. Si and Ge Band Structure on (100) and (110) Longitudinal compression Si Ge Top Bottom Top Bottom (100) (110) hybrid

  15. Full Transport Model: Calculation of Density of States Si is confined in kz direction. 2-dimensional density of state is given by: And total charge density over all possible bands:

  16. Density of States Mass 3 Longitudinal compressive 2.5 0 2 Effective Mass m*/m Production level stress 1.5 1 0.5 Biaxial tensile 0 0.1 1 10 Stress / GPa

  17. Summary / Next Steps • First-principles quantum mechanical methods for strained Si band structure • Spatially dependent strain-induced band structure • Model charge transport and collection due to single event in FLOOPS/FLOODS • Start with existing MURI developed models • Add strain for Si and Ge transistors

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