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Computer Architecture. Lecture 5 Tomasulo’s Algorithm. LD/ST. LD/ST. Wait for Operands. Wait for Operands. EX TAC. EX TAC. Mem Access. Mem Access. DATA. Read Reg. Tag. Integer. Integer. Wait for Operands. Wait for Operands. Wait for Operands. EX. EX. CDB. CDB.

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Computer architecture l.jpg

Computer Architecture

Lecture 5

Tomasulo’s Algorithm


Tomasulo s algorithm l.jpg

LD/ST

LD/ST

Wait for Operands

Wait for Operands

EX

TAC

EX

TAC

Mem

Access

Mem

Access

DATA

Read Reg

Tag

Integer

Integer

Wait for Operands

Wait for Operands

Wait for Operands

EX

EX

CDB

CDB

ISSUE/ Rename to RS

ISSUE/ Rename to RS

FP

FP ADD

Wait for Operands

Wait for Operands

Wait for Operands

A

1

A

1

A

2

A

2

A

3

A

3

A

4

A

4

Write Reg

Write Reg

Check for RS

Wait for Operands

Wait for Operands

Wait for Operands

M

1

M

1

M

2

M

2

..

..

M

7

M

7

Wait for Operands

Wait for Operands

Wait for Operands

Divide

Divide

Check for RAW

Tomasulo’s Algorithm



Loop based example l.jpg
Loop based Example class)

Loop: LD F0,0(R1)

MULTD F4,F0,F2

SD F4,0(R1)

ADDI R1,R1,#-8

BNEZ R1, Loop

This time assume Multiply takes 4 clocks

  • Assume 1st load takes 8 clocks (L1 cache miss), 2nd load takes 1 clock (hit)

  • To be clear, will show clocks for ADDI, BNEZ

    • Reality: integer instructions ahead of Floating Point Instructions

  • Show 2 iterations

  • (Next few slides taken from NET and modified)


Example cont d l.jpg

Iter- class)

ation

Count

Added Store Buffers

Instruction Loop

Value of Register used for address, iteration control

Example Cont’d


Cycle 1 l.jpg
Cycle 1… class)


Cycle 2 l.jpg
Cycle 2… class)


Cycle 3 l.jpg
Cycle 3… class)

Instruction status:

Exec

Write

Fu

ITER

Instruction

j

k

Issue

Comp

Result

Busy

Addr

  • Implicit renaming sets up data flow graph

1

LD

F0

0

R1

1

Load1

Yes

80

1

MULTD

F4

F0

F2

2

Load2

No

1

SD

F4

0

R1

3

Load3

No

Store1

Yes

80

Mult1

Store2

No

Store3

No

Reservation Stations:

S1

S2

RS

Time

Name

Busy

Op

Vj

Vk

Qj

Qk

Code:

Add1

No

LD

F0

0

R1

Add2

No

MULTD

F4

F0

F2

Add3

No

SD

F4

0

R1

Mult1

Yes

Multd

R(F2)

Load1

SUBI

R1

R1

#8

Mult2

No

BNEZ

R1

Loop

Register result status

Clock

F0

F2

F4

F6

F8

F10

F12

...

F30

R1

Fu

3

80

Load1

Mult1


Cycle 4 l.jpg
Cycle 4… class)

  • Dispatching SUBI Instruction (not in FP queue)


Cycle 5 l.jpg
Cycle 5… class)

  • And, BNEZ instruction (not in FP queue)


Loop example cycle 6 l.jpg
Loop Example Cycle 6 class)

  • Notice that F0 never sees Load from location 80


Loop example cycle 7 l.jpg
Loop Example Cycle 7 class)

  • Register file completely detached from computation

  • First and Second iteration completely overlapped



Loop example cycle 9 l.jpg
Loop Example Cycle 9 class)

  • Load1 completing: who is waiting?

  • Note: Dispatching SUBI


Loop example cycle 10 l.jpg
Loop Example Cycle 10 class)

  • Load2 completing: who is waiting?

  • Note: Dispatching BNEZ


Loop example cycle 11 l.jpg
Loop Example Cycle 11 class)

  • Next load in sequence


Loop example cycle 12 l.jpg
Loop Example Cycle 12 class)

  • Why not issue third multiply?


Loop example cycle 13 l.jpg
Loop Example Cycle 13 class)

  • Why not issue third store?


Loop example cycle 14 l.jpg
Loop Example Cycle 14 class)

  • Mult1 completing. Who is waiting?


Loop example cycle 15 l.jpg
Loop Example Cycle 15 class)

  • Mult2 completing. Who is waiting?






Loop example cycle 20 l.jpg
Loop Example Cycle 20 class)

  • Once again: In-order issue, out-of-order execution and out-of-order completion.


Tomasulo s loop based example l.jpg
Tomasulo’s Loop Based Example class)

Multiply Takes 10 Clock Cycles



Example 2 l.jpg
Example 2 class)

Loop:L.D F0, 0(R1)

MULT.D F4, F0, F2

S.D F4, 0(R1)

ADDI R1,R1,-8

c.eq.D F5, F4 ;Compares F5 & F4 & set carry flag if equal

bclt label ; Branch if equal

Assumption:

Processor assumes branch taken policy issues instructions from target address.

Remember: Even an FP instruction can fit into a delay slot


Example 229 l.jpg
Example 2 class)


Tomasulo s loop based example with delayed branching l.jpg
Tomasulo’s Loop Based Example with Delayed Branching class)

After Arrangement

Loop: L.D F0,0(R1)

DADDUI R1,R1,-8

MULT.D F4,F0,F2

BNE R1,R2,Loop

S.D F4,+8(R1)

Loop: L.D F0,0(R1)

MULT.D F4,F0,F2

S.D F4,0(R1)

DADDUI R1,R1,-8

BNE R1,R2,Loop



Why can tomasulo overlap iterations of loops l.jpg
Why can Tomasulo overlap iterations of loops? class)

  • Register renaming

    • Multiple iterations use different physical destinations for registers (dynamic loop unrolling).

  • Reservation stations

    • Permit instruction issue to advance past integer control flow operations

    • Also buffer old values of registers - totally avoiding the WAR stall that we saw in the scoreboard.

  • Other perspective: Tomasulo building data flow dependency graph on the fly.


Tomasulo s scheme offers 2 major advantages l.jpg
Tomasulo’s scheme offers 2 major advantages class)

  • the distribution of the hazard detection logic

    • distributed reservation stations and the CDB

    • If multiple instructions waiting on single result, & each instruction has other operand, then instructions can be released simultaneously by broadcast on CDB

    • If a centralized register file were used, the units would have to read their results from the registers when register buses are available.

      (2) the elimination of stalls for WAWand WAR hazards


What about precise interrupts l.jpg
What about Precise Interrupts? class)

  • State of machine looks as if no instruction beyond faulting instructions has issued

  • Tomasulo had:In-order issue, out-of-order execution, and out-of-order completion

  • Need to “fix” the out-of-order completion aspect so that we can find precise breakpoint in instruction stream.


Tomasulo drawbacks l.jpg
Tomasulo Drawbacks class)

  • Complexity

    • delays of 360/91, MIPS 10000, Alpha 21264, IBM PPC 620 in CA:AQA 2/e, but not in silicon!

  • Many associative stores (CDB) at high speed

  • Performance limited by Common Data Bus

    • Each CDB must go to multiple functional units high capacitance, high wiring density

    • Number of functional units that can complete per cycle limited to one!

      • Multiple CDBs  more FU logic for parallel assoc stores

  • Non-precise interrupts!


Summary l.jpg
Summary class)

  • Reservations stations: implicit register renaming to larger set of registers + buffering source operands

    • Prevents registers as bottleneck

    • Avoids WAR, WAW hazards

    • Allows loop unrolling in HW

  • Not limited to basic blocks (integer units gets ahead, beyond branches)


Summary37 l.jpg
Summary class)

  • Today, helps cache misses as well

    • Don’t stall for L1 Data cache miss (insufficient ILP for L2 miss?)

  • Lasting Contributions

    • Dynamic scheduling and Loop Unrolling

    • Register renaming

    • Load/store disambiguation

  • 360/91 descendants are Pentium III; PowerPC 604; MIPS R10000; HP-PA 8000; Alpha 21264


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