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# Computer Architecture - PowerPoint PPT Presentation

Computer Architecture. Lecture 5 Tomasulo’s Algorithm. LD/ST. LD/ST. Wait for Operands. Wait for Operands. EX TAC. EX TAC. Mem Access. Mem Access. DATA. Read Reg. Tag. Integer. Integer. Wait for Operands. Wait for Operands. Wait for Operands. EX. EX. CDB. CDB.

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### Computer Architecture

Lecture 5

Tomasulo’s Algorithm

LD/ST

Wait for Operands

Wait for Operands

EX

TAC

EX

TAC

Mem

Access

Mem

Access

DATA

Tag

Integer

Integer

Wait for Operands

Wait for Operands

Wait for Operands

EX

EX

CDB

CDB

ISSUE/ Rename to RS

ISSUE/ Rename to RS

FP

Wait for Operands

Wait for Operands

Wait for Operands

A

1

A

1

A

2

A

2

A

3

A

3

A

4

A

4

Write Reg

Write Reg

Check for RS

Wait for Operands

Wait for Operands

Wait for Operands

M

1

M

1

M

2

M

2

..

..

M

7

M

7

Wait for Operands

Wait for Operands

Wait for Operands

Divide

Divide

Check for RAW

Tomasulo’s Algorithm

Loop based Example class)

Loop: LD F0,0(R1)

MULTD F4,F0,F2

SD F4,0(R1)

BNEZ R1, Loop

This time assume Multiply takes 4 clocks

• Assume 1st load takes 8 clocks (L1 cache miss), 2nd load takes 1 clock (hit)

• To be clear, will show clocks for ADDI, BNEZ

• Reality: integer instructions ahead of Floating Point Instructions

• Show 2 iterations

• (Next few slides taken from NET and modified)

Iter- class)

ation

Count

Instruction Loop

Value of Register used for address, iteration control

Example Cont’d

Cycle 1… class)

Cycle 2… class)

Cycle 3… class)

Instruction status:

Exec

Write

Fu

ITER

Instruction

j

k

Issue

Comp

Result

Busy

• Implicit renaming sets up data flow graph

1

LD

F0

0

R1

1

Yes

80

1

MULTD

F4

F0

F2

2

No

1

SD

F4

0

R1

3

No

Store1

Yes

80

Mult1

Store2

No

Store3

No

Reservation Stations:

S1

S2

RS

Time

Name

Busy

Op

Vj

Vk

Qj

Qk

Code:

No

LD

F0

0

R1

No

MULTD

F4

F0

F2

No

SD

F4

0

R1

Mult1

Yes

Multd

R(F2)

SUBI

R1

R1

#8

Mult2

No

BNEZ

R1

Loop

Register result status

Clock

F0

F2

F4

F6

F8

F10

F12

...

F30

R1

Fu

3

80

Mult1

Cycle 4… class)

• Dispatching SUBI Instruction (not in FP queue)

Cycle 5… class)

• And, BNEZ instruction (not in FP queue)

Loop Example Cycle 6 class)

• Notice that F0 never sees Load from location 80

Loop Example Cycle 7 class)

• Register file completely detached from computation

• First and Second iteration completely overlapped

Loop Example Cycle 9 class)

• Load1 completing: who is waiting?

• Note: Dispatching SUBI

Loop Example Cycle 10 class)

• Load2 completing: who is waiting?

• Note: Dispatching BNEZ

Loop Example Cycle 11 class)

Loop Example Cycle 12 class)

• Why not issue third multiply?

Loop Example Cycle 13 class)

• Why not issue third store?

Loop Example Cycle 14 class)

• Mult1 completing. Who is waiting?

Loop Example Cycle 15 class)

• Mult2 completing. Who is waiting?

Loop Example Cycle 20 class)

• Once again: In-order issue, out-of-order execution and out-of-order completion.

Multiply Takes 10 Clock Cycles

Example 2 class)

Loop:L.D F0, 0(R1)

MULT.D F4, F0, F2

S.D F4, 0(R1)

c.eq.D F5, F4 ;Compares F5 & F4 & set carry flag if equal

bclt label ; Branch if equal

Assumption:

Processor assumes branch taken policy issues instructions from target address.

Remember: Even an FP instruction can fit into a delay slot

Example 2 class)

After Arrangement

Loop: L.D F0,0(R1)

MULT.D F4,F0,F2

BNE R1,R2,Loop

S.D F4,+8(R1)

Loop: L.D F0,0(R1)

MULT.D F4,F0,F2

S.D F4,0(R1)

BNE R1,R2,Loop

• Register renaming

• Multiple iterations use different physical destinations for registers (dynamic loop unrolling).

• Reservation stations

• Permit instruction issue to advance past integer control flow operations

• Also buffer old values of registers - totally avoiding the WAR stall that we saw in the scoreboard.

• Other perspective: Tomasulo building data flow dependency graph on the fly.

• the distribution of the hazard detection logic

• distributed reservation stations and the CDB

• If multiple instructions waiting on single result, & each instruction has other operand, then instructions can be released simultaneously by broadcast on CDB

• If a centralized register file were used, the units would have to read their results from the registers when register buses are available.

(2) the elimination of stalls for WAWand WAR hazards

• State of machine looks as if no instruction beyond faulting instructions has issued

• Tomasulo had:In-order issue, out-of-order execution, and out-of-order completion

• Need to “fix” the out-of-order completion aspect so that we can find precise breakpoint in instruction stream.

Tomasulo Drawbacks class)

• Complexity

• delays of 360/91, MIPS 10000, Alpha 21264, IBM PPC 620 in CA:AQA 2/e, but not in silicon!

• Many associative stores (CDB) at high speed

• Performance limited by Common Data Bus

• Each CDB must go to multiple functional units high capacitance, high wiring density

• Number of functional units that can complete per cycle limited to one!

• Multiple CDBs  more FU logic for parallel assoc stores

• Non-precise interrupts!

Summary class)

• Reservations stations: implicit register renaming to larger set of registers + buffering source operands

• Prevents registers as bottleneck

• Avoids WAR, WAW hazards

• Allows loop unrolling in HW

• Not limited to basic blocks (integer units gets ahead, beyond branches)

Summary class)

• Today, helps cache misses as well

• Don’t stall for L1 Data cache miss (insufficient ILP for L2 miss?)

• Lasting Contributions

• Dynamic scheduling and Loop Unrolling

• Register renaming