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Negative Number Representation in Computer Systems

Learn about representing negative numbers in computers, including sign and magnitude, one's complement, two's complement, and shortcuts for negation and sign extension. Understand binary addition and full adder circuits.

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Negative Number Representation in Computer Systems

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  1. Number Representation

  2. How to Represent Negative Numbers? • So far, unsigned numbers • Obvious solution: define leftmost bit to be sign! • 0 => +, 1 => - • Rest of bits can be numerical value of number • Representation called sign and magnitude

  3. Shortcomings of sign and magnitude? • Arithmetic circuit more complicated • Special steps depending whether signs are the same or not • Also, Two zeros • 0x00000000 = +0ten • 0x80000000 = -0ten • What would it mean for programming? • Sign and magnitude abandoned

  4. 00000 00001 ... 01111 11111 10000 ... 11110 Another try: complement the bits • Example: 710 = 001112 -710 = 110002 • Called one’s Complement • Note: postive numbers have leading 0s, negative numbers have leadings 1s. • What is -00000 ? • How many positive numbers in N bits? • How many negative ones?

  5. Shortcomings of ones complement? • Arithmetic not too hard • Still two zeros • 0x00000000 = +0ten • 0xFFFFFFFF = -0ten • What would it mean for programming? • One’s complement eventually abandoned because another solution was better

  6. Search for Negative Number Representation • Obvious solution didn’t work, find another • What is result for unsigned numbers if tried to subtract large number from a small one? • Would try to borrow from string of leading 0s, so result would have a string of leading 1s • With no obvious better alternative, pick representation that made the hardware simple: leading 0s  positive, leading 1s  negative • 000000...xxx is >=0, 111111...xxx is < 0 • This representation called two’s complement

  7. Two’s Complement Number line 00000 11111 • 2 N-1 non-negatives • 2 N-1 negatives • one zero • how many positives? • comparison? • overflow? 00001 11110 00010 0 -1 1 2 -2 . . . . . . 15 -15 -16 01111 10001 10000

  8. Two’s Complement Numbers 0000 ... 0000 0000 0000 0000two = 0ten0000 ... 0000 0000 0000 0001two = 1ten0000 ... 0000 0000 0000 0010two = 2ten. . .0111 ... 1111 1111 1111 1101two = 2,147,483,645ten0111 ... 1111 1111 1111 1110two = 2,147,483,646ten0111 ... 1111 1111 1111 1111two = 2,147,483,647ten1000 ... 0000 0000 0000 0000two = –2,147,483,648ten1000 ... 0000 0000 0000 0001two = –2,147,483,647ten1000 ... 0000 0000 0000 0010two = –2,147,483,646ten. . . 1111 ... 1111 1111 1111 1101two = –3ten1111 ... 1111 1111 1111 1110two = –2ten1111 ... 1111 1111 1111 1111two = –1ten • One zero, 1st bit => >=0 or <0, called sign bit • but one negative with no positive –2,147,483,648ten

  9. Two’s Complement Formula • Can represent positive and negative numbers in terms of the bit value times a power of 2: • d31 x -231+ d30 x 230 + ... + d2 x 22 + d1 x 21 + d0 x 20 • Example1111 1111 1111 1111 1111 1111 1111 1100two = 1x-231+1x230 +1x229+...+1x22+0x21+0x20 = -231+ 230 + 229 + ...+ 22 + 0 + 0 = -2,147,483,648ten + 2,147,483,644ten = -4ten • Note: need to specify width: we use 32 bits

  10. Two’s complement shortcut: Negation • Invert every 0 to 1 and every 1 to 0, then add 1 to the result • Sum of number and its one’s complement must be 111...111two • 111...111two= -1ten • Let x’ mean the inverted representation of x • Then x + x’ = -1  x + x’ + 1 = 0  x’ + 1 = -x • Example: -4 to +4 to -4x : 1111 1111 1111 1111 1111 1111 1111 1100twox’: 0000 0000 0000 0000 0000 0000 0000 0011two+1: 0000 0000 0000 0000 0000 0000 0000 0100two()’: 1111 1111 1111 1111 1111 1111 1111 1011two+1: 1111 1111 1111 1111 1111 1111 1111 1100two

  11. Two’s comp. shortcut: Sign extension • Convert 2’s complement number using n bits to more than n bits • Simply replicate the most significant bit (sign bit) of smaller to fill new bits • 2’s comp. positive number has infinite 0s • 2’s comp. negative number has infinite 1s • Bit representation hides leading bits; sign extension restores some of them • 16-bit -4ten to 32-bit: 1111 1111 1111 1100two 1111 1111 1111 1111 1111 1111 1111 1100two

  12. Addition of Positive Numbers

  13. Carries a: 0 0 1 1 b: 0 1 0 1 Sum: 1 0 0 0 One-Bit Full Adder (1/3) • Example Binary Addition: • Thus for any bit of addition: • The inputs are ai, bi, CarryIni • The outputs are Sumi, CarryOuti • Note: CarryIni+1 = CarryOuti

  14. Definition Sum = ABCin + ABCin + ABCin + ABCin CarryOut = AB + ACin + BCin ¯ ¯ ¯ ¯ ¯ ¯ One-Bit Full Adder (2/3)

  15. CarryIn A + Sum B CarryOut One-Bit Full Adder (3/3) • To create one-bit full adder: • implement gates for Sum • implement gates for CarryOut • connect all inputs with same name

  16. Ripple-Carry Adders: adding n-bits numbers CarryIn0 • Critical Path of n-bit Rippled-carry adder is n*CP • CP = 2 gate-delays (Cout = AB + ACin + BCin) A0 1-bit FA Sum0 B0 CarryOut0 CarryIn1 A1 1-bit FA Sum1 B1 CarryOut1 CarryIn2 A2 1-bit FA Sum2 B2 CarryOut2 CarryIn3 A3 1-bit FA Sum3 B3 CarryOut3

  17. Fast Adders

  18. Cin A B C-out 0 0 0 “kill” 0 1 C-in “propagate” 1 0 C-in “propagate” 1 1 1 “generate” A0 S0 G B0 P C1 =G0 + C0· P0 = A0B0 + C0(A0+B0) A S P = A + B G = A  B G B P C2 = G1 + G0 · P1 + C0· P0 · P1 A S G B P C3 = G2 + G1 · P2 + G0 · P1 · P2 + C0· P0 · P1 · P2 A S G = G3 + P3·G2 + P3·P2·G1 + P3·P2·P1·G0 G B P P = P3·P2·P1·P0 C4 = . . . Carry Look Ahead: reducing Carry Propagation delay

  19. ¯ ¯ ¯ ¯ ¯ ¯ Sum = ABCin + ABCin + ABCin + ABCin Carry Look Ahead: Delays • Expression for any carry: • Ci+1 = Gi + PiGi-1 + … + PiPi-1 … P0C0 • All carries can be obtained in 3 gate-delays: • 1 needed to developed all Pi and Gi • 2 needed in the AND-OR circuit • All sums can be obtained in 6 gate-delays: • 3 needed to obtain carries • 1 needed to invert carry • 2 needed in the AND-OR circuit of Sum’s circuit • Independent of the number of bits (n) • 4-bit Adder: • CLA: 6 gate-delays • RC: (3*2 + 3) gate-delays • 16-bit Adder: • CLA: 6 gate-delays • RC: (15*2 + 3) gate-delays

  20. C L A 4-bit Adder 4-bit Adder 4-bit Adder Cascaded CLA: overcoming Fan-in constraint C0 G0 P0 C1 =G0 + C0 · P0 Delay = 3 + 2 + 3 = 8 DelayRC = 15*2 + 3 = 33 C2 = G1 + G0 · P1 + C0 · P0 · P1 C3 = G2 + G1 · P2 + G0 · P1 · P2 + C0 · P0 · P1 · P2 G P C4 = . . .

  21. Signed Addition & Subtraction

  22. Addition & Subtraction Operations • Addition: • Just add the two numbers • Ignore the Carry-out from MSB • Result will be correct, provided there’s no overflow • Subtraction: • Form 2’s complement of the subtrahend • Add the two numbers as in Addition 0 1 0 1 (+5)+0 0 1 0 (+2) 0 1 1 1 (+7) 0 1 0 1 (+5)+1 0 1 0 (-6) 1 1 1 1 (-1) 0 0 1 0 (+2) 0 0 1 00 1 0 0 (+4) +1 1 0 0 (-4) 1 1 1 0 (-2) 1 0 1 1 (-5)+1 1 1 0 (-2)11 0 0 1 (-7) 0 1 1 1 (+7)+1 1 0 1 (-3)10 1 0 0 (+4) 1 1 1 0 (-2) 1 1 1 01 0 1 1 (-5) +0 1 0 1 (+5)10 0 1 1 (+3)

  23. Overflow Decimal Binary Decimal 2’s Complement 0 0000 0 0000 • Examples: 7 + 3 = 10 but ... • - 4  5 = - 9 but ... 1 0001 -1 1111 2 0010 -2 1110 3 0011 -3 1101 4 0100 -4 1100 5 0101 -5 1011 6 0110 -6 1010 7 0111 -7 1001 -8 1000 0 1 1 1 1 0 1 1 1 7 1 1 0 0 – 4 3 – 5 + 0 0 1 1 + 1 0 1 1 1 0 1 0 – 6 0 1 1 1 7

  24. Overflow Detection • Overflow: the result is too large (or too small) to represent properly • Example: - 8 < = 4-bit binary number <= 7 • When adding operands with different signs, overflow cannot occur! • Overflow occurs when adding: • 2 positive numbers and the sum is negative • 2 negative numbers and the sum is positive • On your own: Prove you can detect overflow by: • Carry into MSB ° Carry out of MSB 0 1 1 1 1 0 0 1 1 1 7 1 1 0 0 –4 3 – 5 + 0 0 1 1 + 1 0 1 1 1 0 1 0 – 6 0 1 1 1 7

  25. CarryIn1 A1 1-bit FA Result1 B1 CarryOut1 Overflow Detection Logic • Carry into MSB ° Carry out of MSB • For a N-bit Adder: Overflow = CarryIn[N - 1] XOR CarryOut[N - 1] CarryIn0 A0 1-bit FA Result0 X Y X XOR Y B0 0 0 0 CarryOut0 0 1 1 1 0 1 1 1 0 CarryIn2 A2 1-bit FA Result2 B2 CarryIn3 Overflow A3 1-bit FA Result3 B3 CarryOut3

  26. Arithmetic & Branching Conditions

  27. Condition Codes • CC Flags will be set/cleared by arithmetic operations: • N (negative): 1 if result is negative (MSB = 1), otherwise 0 • C (carry): 1 if carry-out(borrow) is generated, otherwise 0 • V (overflow): 1 if overflow occurs, otherwise 0 • Z (zero): 1 if result is zero, otherwise 0 0 1 0 1 (+5)+0 1 0 0 (+4) 1 0 0 1 (-7?) 0 1 0 1 (+5)+1 0 1 0 (-6)1 1 1 1 (-1) 0 0 1 1 (+3)+1 1 0 1 (-3)10 0 0 0 (0) 0 1 1 1 (+7)+1 1 0 1 (-3)10 1 0 0 (+4)

  28. Multiplication of Positive Numbers

  29. Unsigned Multiplication • Paper and pencil example (unsigned): Multiplicand 1101 (13)Multiplier1011 (11) 11011101 00001101Product 10001111 (143) • m bits x n bits = m+n bit product • Binary makes it easy: • 0 => place 0 ( 0 x multiplicand) • 1 => place a copy ( 1 x multiplicand)

  30. 0 0 0 0 A3 A2 A1 A0 B0 A3 A2 A1 A0 B1 A3 A2 A1 A0 B2 A3 A2 A1 A0 B3 P7 P6 P5 P4 P3 P2 P1 P0 Unsigned Combinational Multiplier • Stage i accumulates A * 2 i if Bi == 1

  31. A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 How does it work? 0 0 0 0 0 0 0 B0 • at each stage shift A left ( x 2) • use next bit of B to determine whether to add in shifted multiplicand • accumulate 2n bit partial product at each stage B1 B2 B3 P7 P6 P5 P4 P3 P2 P1 P0

  32. Multiplier Circuit 4 bits Multiplicand 0 Multiplicand 1101 C ProductMultiplier0 0000 10110 1101 1011 Add0 0110 1101 Shift 1 0011 1101 Add0 1001 1110 Shift 0 1001 1110 NoAdd0 0100 1111 Shift 1 0001 1111 Add0 1000 1111 Shift MUX Shift Right Control 4-bit FA Add/NoAdd C Product (Multiplier) 8 bits 4 bits

  33. Signed-Operand & Multiplication

  34. Signed Multiplication • Negative Multiplicand: Multiplicand 10011 (-13)Multiplier 01011 (+11)1111110011111110011000000001110011000000Product 1101110001 (-143) • Negative Multiplier: • Form 2’s complement of both multiplier and multiplicand • Proceed as above

  35. Motivation for Booth’s Algorithm • Works well for both Negative & Positive Multipliers • Example 2 x 6 = 0010 x 0110: 0010 x 0110 + 0000 shift (0 in multiplier) + 0010 add (1 in multiplier) + 0100 add (1 in multiplier) + 0000 shift (0 in multiplier) 00001100 • FA with add or subtract gets same result in more than one way: 6 = – 2 + 8 0110 = – 00010 + 01000 = 11110 + 01000 • For example • 0010 x 0110 00000000shift (0 in multiplier) 1111110 sub(first 1 in multpl.)000000shift (mid string of 1s) + 00010 add (prior step had last 1) 00001100

  36. Booth’s Algorithm Current Bit Bit to the Right Explanation Example Op 1 0 Begins run of 1s 0001111000 sub 1 1 Middle of run of 1s 0001111000 none 0 1 End of run of 1s 0001111000 add 0 0 Middle of run of 0s 0001111000 none Originally for Speed (when shift was faster than add) • Small number of additions needed when multiplier has a few large blocks of 1s

  37. Booths Example (2 x 7) Operation Multiplicand Product next? 0. initial value 0010 0000 0111 0 10 -> sub 1a. P = P - m 1110 + 1110 1110 0111 0 shift P (sign ext) 1b. 0010 1111 00111 11 -> nop, shift 2. 0010 1111 10011 11 -> nop, shift 3. 0010 1111 11001 01 -> add 4a. 0010 + 0010 0001 11001 shift 4b. 0010 0000 1110 0 done

  38. Booths Example (2 x -3) Operation Multiplicand Product next? 0. initial value 0010 0000 1101 0 10 -> sub 1a. P = P - m 1110 + 1110 1110 1101 0 shift P (sign ext) 1b. 0010 1111 01101 01 -> add + 0010 2a. 0001 01101shift P 2b. 0010 0000 10110 10 -> sub + 1110 3a. 0010 1110 10110 shift 3b. 0010 1111 0101 1 11 -> nop 4a 1111 0101 1 shift 4b. 0010 1111 10101 done

  39. Fast Multiplication (read yourself!)

  40. Integer Division

  41. Divide: Paper & Pencil 1001 Quotient Divisor 1000 1001010 Dividend–1000 10 101 1010–1000 10 Remainder (or Modulo result) • See how big a number can be subtracted, creating quotient bit on each step Binary => 1 * divisor or 0 * divisor • Dividend = Quotient x Divisor + Remainder=> | Dividend | = | Quotient | + | Divisor |

  42. Divisor Division Circuit 33 bits Shift Left Control 33-bit FA Q Setting Remainder (Quotient) 65 bits 33 bits Sign-bit Checking

  43. 0010QuotientDivisor11 1000 Dividend 1110Remainder Restoring Division Algorithm RemainderQuotient Initially 00000 1000Shift 00001 000_Sub(-11) 11101Set q0 11110Restore 00001 0000 Shift 00010 000_Sub(-11) 11101Set q0 11111Restore 00010 0000 Shift 00100 000_Sub(-11) 11101Set q0 00001 00001 0001 Shift 00010 001_Sub(-11) 11101 001_Set q0 11111Restore 00010 0010

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