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Engineering Models and Circuit Realization of Quantum State Machines

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5.1. Complete Automated System for Design of QSM

- Use state minimization/state assignment techniques available in the Berkeley tools to obtain various encoded ( and/or minimized ) flavors of the machine
- Use DCARL/MMD to find the reversible logic solutions for all flavors of the encoded machine
- Analyze the results and come up with the best state minimization / encoding strategy that works for reversible logic implementation of the FSM
- Use the Benchmark circuits for the input FSM’s

Problem Definition

- State assignment problem
- Involves assigning binary coded values to the states of an FSM
- The target is to minimize the area of the combinational circuit required to realize the FSM
- The complexity of the combinational component of the FSM depends heavily on the state assignment and selection of memory elements
- Creating completely specified functions
- Done by assigning values to the “don’t care” outputs to produce reversible logic

Tools and Flow

- Available Berkeley tools – MVSIS, SIS, VIS
- SIS – System for Sequential circuit synthesis
- MVSIS – for multiple valued logic synthesis, does not implement sequential logic yet
- VIS – Verification tool for sequential logic, calls SIS to do the optimization for any given state machine
- SIS available 1.2 for Windows and 1.3 for Linux
- Can be downloaded from http://embedded.eecs.berkeley.edu/pubs/downloads/sis/index.htm

Tools and Flow

- DCARL – Don’t Care algorithm for reversible logic, developed at PSU in 2007 and presented at RM 2007
- Assign values to the “don't cares” outputs, and map the outputs according to the assigned input values, creating thus a completely specified reversible Boolean function specification
- Apply the MMD algorithm to this specification to synthesize the network
- Compare the cost in terms of the number of Toffoli gates and keep track of the “don't cares” values with the minimal cost
- Backtrack to find K solutions or until no more backtracking is possible

SIS Usage

- Inputs can be in KISS, BLIF format
- KISS – uses State Transition Graph format, can be synchronous as well as asynchronous
- BLIF – Netlist of Combinational gates and latches
- BLIF – internally represented as care network, don’t care network, can be verified by stg_cover command which simulates both symbolically
- Performs State minimization, State assignment, Retiming

SIS commands and description

- State minimization – states are equivalent if they produce same outputs for same set of inputs
- Uses STAMINA, developed by University of Colorado, Boulder with heuristics implemented for incompletely specified machines
- Uses KISS input and output
- State assignment – STG to binary codes for each symbolic state
- Retiming – moves registers across logic gates to minimize cycle time, number of registers

State assignment toolsSIS - NOVA

- Target two-level PLA based implementations
- Optimizes the number of product terms called cubes
- The assignment needs to be in such a way that the area of the combinational circuit required to realize the FSM is minimized
- Solves two types of problems:
- Constrained cubical embedding problem
- Focused on input constraints
- Covered constrained cubical embedding problem
- Focused on both input and output constraints

NOVAAlgorithms used for state encoding

- Algorithms that solve constrained cubical embedding problem:
- iexact_code
- Is an exact algorithm
- Finds an encoding satisfying all input constraints
- Target is minimizing the encoding length
- ihybrid_code
- heuristic encoding algorithms (approximate)
- Target is to maximize input constraint satisfaction
- User supplied encoding length (or default used)
- Based on a polynomial version of iexact_code
- Yields solutions of high quality and guarantees the satisfaction of all input constraints for an encoding space large enough

NOVAAlgorithms used for state encoding

- igreedy_code
- Heuristic encoding algorithms (approximate)
- Target is to maximize input constraint satisfaction
- User supplied encoding length (or default used)
- Specially tailored for short code-lengths
- Algorithm that solves covered constrained cubical embedding problem:
- iohybrid_code
- heuristic encoding algorithms (approximate)
- Target is to maximizes simultaneous input and output constraint satisfaction
- Based on an adaptation of ihybrid_code to deal with both input and output constraints

State assignment tools:SIS - Jedi

- Target multi-level logic implementations
- Uses simulated annealing based encoding scheme
- There are four main heuristics for generating weights between pairs of states:
- Input dominant
- Output dominant
- Coupled
- Variations

JediAlgorithms used for state encoding

- The input dominant algorithm:
- works on the source states of the transitions of the FSMs (the states from which the transitions are triggered)
- pairs of present states which assert similar outputs and produce similar sets of next states are given high edge weights
- This has an effect of maximizing the size of common cubes in the boolean functions corresponding to the output and the next state lines
- The output dominant algorithm
- works on the output states of the transitions of the FSMs
- pairs of next states which are produced by similar inputs and similar sets of present states are given high edge weights
- This has an effect of maximizing the number of common cubes in the boolean functions corresponding to the next state lines
- The coupled approach
- Uses a hybrid of the input and output dominant heuristics
- Variations
- Examples: one-hot, random, straight mapping

Input state machine

.i 1

.o 1

.p 10

.s 5

0 A B 0

1 A C 1

0 B C 1

1 B B 0

0 C C 1

1 C D 1

0 D E 1

1 D A 1

0 E B 0

1 E C 1

SIS example flow- Encoded State Machine – part of BLIF output
- 0 S0 S1 0
- 1 S0 S2 1
- 0 S1 S2 1
- 1 S1 S1 0
- 0 S2 S2 1
- 1 S2 S3 1
- 0 S3 S0 1
- 1 S3 S0 1
- .code S0 11
- .code S1 10
- .code S2 00
- .code S3 01

Minimized State Machine

.i 1

.o 1

.p 8

.s 4

.r S0

0 S0 S1 0

1 S0 S2 1

0 S1 S2 1

1 S1 S1 0

0 S2 S2 1

1 S2 S3 1

0 S3 S0 1

1 S3 S0 1

DCARL Usage/Description

- Inputs are test files that contains input vectors
- Input bits can be 0, 1 or x
- Outputs are text files, one for each solution, output file contains output vectors that are output bits
- Output bits can only be 0 or 1 (completely specified)
- No repeated output vectors (reversible)
- Some bits may be added to generate reversible functions
- Outputs of DCARL applied to MMD to choose best solution

Incompletely

Specified

Input

001

101

11x

00x

01x

xx0

xxx

111

DCARL example flow 1Completely

Specified

Output 1

001

101

110

000

010

100

011

111

Completely

Specified

Output 2

001

101

110

000

011

010

100

111

Incompletely

Specified

Input

001

001

11x

00x

01x

xx0

xxx

111

DCARL example flow 2/1- Add Garbage bitsGenerate reversible logic bits

Output 1

0001

1001

0110

0000

0010

0100

0011

0111

0101

1000

1010

1011

1100

1101

1110

1111

Output 2

1001

0001

0110

0000

0010

0100

0011

0111

0101

1000

1010

1011

1100

1101

1110

1111

DCARL example flow 2/2

- Add Garbage bitsGenerate reversible logic bits

Output 3

0001

1001

0111

0000

0010

0100

0011

1111

0101

0110

1001

1010

1011

1100

1101

1110

Output 4

0001

1001

1110

0000

0010

0100

0011

0111

0101

0110

1000

1010

1011

1100

1101

1111

Output 5

0001

1001

1111

0000

0010

0100

0011

0111

0101

0110

1000

1010

1011

1100

1101

1110

Output 6

0001

1001

0110

1000

0010

0000

0011

0111

0100

0101

1010

1011

1100

1101

1110

1111

SIS output to DCARL input conversion

DCARL format

Only outputs in the input file

Inputs included here for clarity

Format below

Encoded State, Input / Output

000 - 001

001 - 011

010 - 111

011 - 111

100 - 001

101 - 100

110 - 100

111 - 001

Encoded State Machine

0 S0 S1 0

1 S0 S2 1

0 S1 S2 1

1 S1 S1 0

0 S2 S2 1

1 S2 S3 1

0 S3 S0 1

1 S3 S0 1

.code S0 11

.code S1 10

.code S2 00

.code S3 01

6.1. Results - Work flow

- Some FSM’s from MCNC benchmark circuits chosen
- SIS – State machine minimization run on each circuits
- State assignment - NOVA and JEDI with options run on all the circuits
- DCARL input file for each encoded state machine obtained
- DCARL run on the input and cost obtained

6.2. Conclusions on Software

- Different algorithms for state assignment and Boolean function realization of excitation functions provide minimal cost for different state machines
- Some options like “ie” works better with smaller circuits, but bigger circuits it either add extra bits or even fail
- In almost 70% of the cases the random or coupled approaches gave the best results for Jedi
- In general Jedi is better in handling bigger circuits compared to Nova
- Both Nova and Jedi are algorithms developed in past for SOP realization of excitation functions. One needs new state assignments algorithms for ESOP-type of logic, as it is realized in quantum circuits.

7. General Conclusions on QSM Synthesis

- Practical models for QSMs and their classical controllers have been developed. Our approaches all involve state minimization and state assignment of machines. Other methods of realization that are used in classical machines, such as decomposition or one-hot encoding, should be also investigated.
- A synthesis flow which allows us to design QSMs from abstract specifications has been developed. The CAD tool can be improved by improving backtracking method to convert incomplete to complete functions and by better quantum circuit minimizer that will replace MMD.
- Synchronous as well as asynchronous techniques for high level synthesis of QSMs have been demonstrated by us. More details can be found in MS thesis of Manjith Kumar.
- State assignment tools from U.C. Berkeley were used but new algorithms specific to reversible logic should be developed

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