ABC Asynchronous Bit-stream Compression

1. MATRICS Research Group Technion – Israel Institute of Technology ABCAsynchronous Bit-stream Compression Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar MATRICS Research Group, Electrical Engineering Department Technion – Israel Institute of Technology Haifa, Israel

2. Background & Motivation

3. Synchronous Serial Link Fast Clock generation is problematic Sensitive to timing uncertainty on chip

4. Asynchronous Serial Link • Fast operation • No need for clock •  Insensitive to timing uncertainty

5. solution Compression Motivation Limited Bandwidth Asynchronous Bit-stream Compression (ABC)

6. ABC Concept

7. Asynchronous Signaling Data 0 1 0 1 1 0 0 1 0 1 1 1 Level Encoded Dual Rail • Each bit on two wires • One wire (S) is the state (0, 1) • The other wire (P) helps with phase • To change from one value to the next: • If different value, toggle S • If same value, toggle P • Only one wire toggles • No need for Clock! S 0 1 0 1 1 0 0 1 0 1 1 1 LEDR P 0 0 0 0 1 0 1 0 0 0 1 0

8. ABC Concept Data 0 1 0 1 1 0 0 1 0 1 1 1 Level Encoded Dual Rail • Each bit on two wires • One wire (S) is the state (0, 1) • The other wire (P) helps with phase • To change from one value to the next: • If different value, toggle S • If same value, toggle P • Only one wire toggles • No need for Clock! What if… both signals would toggle? S 0 1 0 1 1 0 0 1 0 1 1 1 LEDR P 0 0 0 0 1 0 1 0 0 0 1 0

9. ABC Concept The new transitions can be used for: Asynchronous Bit-stream Compression • Identify a sequence of identical bits • Mark the beginning of the sequence by one of the ABC transitions • Transmit the length of the sequence • Mark the end of the encoding by one of the ABC transitions.

10. 1 0 1 1 0 1 1 0 1 1 S 0 1 0 1 1 0 0 1 0 0 1 1 1 ABC ticks saved P 0 0 0 0 1 0 1 0 0 1 1 0 0 Example of ABC Savings sequence Data 0 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 S 0 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 LEDR P 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 Transmission starts in regular LEDR mode Beginning of compression is marked by ABC transition The length of the sequence is encoded and transmitted The end of the compression is marked by ABC transition Transmission continues in regular LEDR mode

11. ABC Architecture

12. ABC Transmitter

13. ABC Transmitter • Sequence Detectors • Scan Windows • Eight 2-bit XORs • XORs compare sequent bits • Sequence Detectors • Identify sequences • Store the indices and lengths in sequence registers

14. ABC Transmitter • Controller • Sequence Stapler • Combines sequences • Produce final indices • Controller • Signals when compression starts and ends • Transmits the sequence length • Moves the pointer of MUX to next bit after the sequence

15. ABC Transmitter • ABC State Machine • LEDR mode • Standard protocol • One signal toggles each time • ABC mode • Compression performed • ABC activated by Controller • ABC transitions symbolize the start and the end of compression

16. ABC Receiver

17. ABC Receiver • Clock Generator • Translates the transitions in S and P signals into clock pulses. • Synchronizes the data storage in the register, controls the FSM. • Identify the ABC transitions used for compression beginning. • Toggles the input to FSM when ABC starts, switching to a different operation mode.

18. ABC Receiver • Enabling Decoder • Converts the data from serial to parallel. • Provides enable signals to all cells for data storage • In LEDR only one cell is enabled in every cycle • In ABC multiple cells are enabled according to from and till indices. • All the cells in ABC get the same value in one cycle - fast storage

19. ABC Receiver Receiver FSM • Count mode • With each clock an internal counter is increased by one. • The counter controls the enabling decoder. • Comp_Decode mode • Activated when ABC identified • Stable while the sequence length code is received • Comp_Decode mode • Activated when the length is received • Creates the from and till signals for Enabling Decoder • Returns to Count at next clock

20. Design Considerations Alternative Trade-offs our architecture

21. Results

22. ABC in Random Packets • ABC system - transmitter, receiver and 32-bit registers - was designed using VHDL • Transmission time evaluation of the uncompressed packet was 655ns • For maximal compression rate, the transmission time was reduced by 55% to 295ns Simulation of ABC with a series of 100 random packets with various number and lengths of sequences

23. Image Transmission by ABC Images with various differentiation were used for ABC effectiveness evaluation

24. Summary • Asynchronous Bit-stream Compression proposed • ABC targets improvement of BW utilization • Significant saving in transmission time and power • ABC interfaces were implemented and simulated • Number of transitions was reduced by up to 54%

25. Questions?