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Flash

Flash. Qing Xu Tie Chen. Flash. An electronic device Non-volatile Can be electrically erased and reprogrammed Usage: Digital Music Device Smartphones Digital Cameras Removable Storage Devices. (picpedia.com). Non-Volatile Memory. Non-Volatile Memory in Embedded System:

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Flash

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  1. Flash Qing Xu Tie Chen

  2. Flash An electronic device Non-volatile Can be electrically erased and reprogrammed Usage: Digital Music Device Smartphones Digital Cameras Removable Storage Devices (picpedia.com)

  3. Non-Volatile Memory Non-Volatile Memory in Embedded System: • Stores data after power down • Battery Change • Consumer Electronics

  4. Flash Non-Volatile Memory Read-Only: ROM Read-Write: EPROM, E2PROM, FLASH (Figure Credit: Prof. Dennis Sylvester)

  5. Flash Flash Development vs. Moore’s Law (Figure Credit: H. Cho, Stanford University)

  6. MOSFET How does a MOSFET transistor work? (Wikipedia - Threshold formation in MOSFET)

  7. Flash How is Flash different from MOSFET? (Figure Credit: Prof. Grishman, CSCI Inc.)

  8. Flash Operations Writes a Logic ONE Writes a Logic ZERO (Figure Credit: S. Verna, Stanford University)

  9. Flash Wearing Erosion of a flash memory • Programming and erasing breaks down the oxide layer in the transistor. • Life of 100,000 Program/Erase cycles (Figure Credit: Prof. Li-Ping Zhang)

  10. Flash Wearing Flash Memory Controller • Arrange data so that programming/ erasing is distributed evenly • A block of extended life memory is allocated for the controller, stores operation data. Flash Wear Leveling Algorithm: • Dynamic • Static

  11. Flash Wear Leveling Dynamic Wear Leveling: - Controller selects new free data block before write - Mapping points to new block location after write Disadvantage: - Static blocks where data do not change (eg. OS file) wears slower than other blocks - Reduce lifespan of the flash drive

  12. Flash Wear Leveling Static Wear Leveling: - Works the same as dynamic wear leveling - Static blocks that do not change are periodically moved Disadvantage: - Moving static blocks takes time

  13. Flash Wear Leveling Dynamic vs. Static What to use? Use Both!

  14. Introduction to AT45DB161D

  15. Important Facts • 4,096 Pages (512/528 Bytes/Page) Main Memory (2MB in total) • Single 2.5V - 3.6V or 2.7V - 3.6V Supply • SPI Serial Port Interface • Mode 0 and Mode 3 compatible • Two SRAM Data Buffers (512/528 Bytes) • 100,000 Program/Erase Cycles Per Page Minimum

  16. Block Diagram (Figure Credit: AT45DB161D Datasheet)

  17. Pin Configuration

  18. SPI Interface • A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location.

  19. Read Operations • Main Memory Page Read • Buffer Read • Main Memory Page to Buffer Transfer (Figure Credit: AT45DB161D Datasheet)

  20. Write Operations • Buffer Write • Buffer to Main Memory Page Program (Figure Credit: AT45DB161D Datasheet)

  21. Erase Operations • Page Erase (528/512 bytes) • Block Erase (8 pages) • Sector Erase (256 pages) • Chip Erase (all 16 sectors, which is 2MB)

  22. Modifying Data in Flash (Figure Credit: AT45DB161D Datasheet)

  23. Why do We need Buffers? Because it saves us a lot of trouble! • The minimum size of erase/programming is one page. • You will have to send exactly one page data through SPI for every write operation without buffers. • You may have to first send back one page data from flash even before that!

  24. Timing Issues • Erase and Program time • Flash output delay • Setup time, hold time of all serial port … You are able to find timing diagrams and characteristic tables in datasheet. (Figure Credit: AT45DB161D Datasheet)

  25. Power Issues • 7 mA Active Read Current Typical • 12 mA Active Program/Erase Current Typical • 25 μA Standby Current Typical • 9 μA Deep Power Down Typical (Figure Credit: AT45DB161D Datasheet)

  26. Other Features • Software Sector Protection • Sector Lockdown • Status Register • Security Register • Deep Power-down and Resume • Page Size Option

  27. Reference • http://www.eeherald.com/section/design-guide/esmod16.html • http://digitalelectronics.blogspot.com/2009/10/flash-memroies-introduction.html • http://picpedia.com/flash-memory-cards • S. Verma, “Tunnel Barrier Engineering for Flash Memory Technology”, Stanford University, May 2010 • H. Cho, “Low Power, Highly Scalable, Vertical Flash Memory Cell and MOSFET”, Stanford University, Sept 2007 • ATMEL, AT45DB161D 16-megabit DataFlashSpecification • L.P. Zhang, “Low Cost Wearing Algorithm for Block Mapping Solid State Disks”, National Chiao‐Tung University, Taiwan

  28. Questions?

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