1 / 1

A Reconfigurable Coprocessor for Finite Field Multiplications in GF(2 )

A Reconfigurable Coprocessor for Finite Field Multiplications in GF(2 ). n. Polynomial Karatsuba multiplication. Recursive construction process. Atmel AT94K FPSLIC architecture. Layers of an EC based cryptosystem. Generic Coprocessor architecture. Elliptic curve point addition.

Download Presentation

A Reconfigurable Coprocessor for Finite Field Multiplications in GF(2 )

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. A Reconfigurable Coprocessor for Finite Field Multiplications in GF(2 ) n Polynomial Karatsuba multiplication Recursive construction process Atmel AT94K FPSLIC architecture Layers of an EC based cryptosystem Generic Coprocessor architecture Elliptic curve point addition Karatsuba Multiplier gate count Michael Jung, Felix Madlener, Markus Ernst and Sorin A. Huss Integrated Circuits and Systems LabComputer Science DepartmentDarmstadt University of Technology, Germany Summary The performance of elliptic curve based public key cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. This work describes a reconfigurable finite field multiplier, which is implemented within the latest family of Field Programmable System Level Integrated Circuits from Atmel, Inc. The architecture of the coprocessor is adapted from Karatsuba‘s divide and conquer algorithm and allows for a reasonable speedup of the top-level public key algorithms. The VHDL hardware models are automatically generated based on an eligible operand size, which permits the optimal utilization of a particular FPSLIC device.

More Related