How caches take advantage of Temporal locality

1. How caches take advantage of Temporal locality

2. How caches take advantage of Spatial locality

3. Cache Hits

4. Cache Misses

5. Cache Design

6. Mapping schemes • Direct Mapped • Set Associative • Fully Associative

7. Each main memory address maps to exactly one cache block Here is 16-byte main memory and a 4-byte cache (four 1-byte blocks) Memory locations 0, 4, 8 and 12 map to cache block 0 1, 5, 9 and 13 to cache block 1 Direct Mapped

8. One way to use the mod operator (reminder) If a cache contains 2k blocks, then data at memory address i would go to cache block index i mod 2k  address 14 maps to cache block 2 14 mod 4 = 2 How to map a memory address

9. Another way is to look at the least significant k bits of the address With 4-byte cache we would inspect the two least significant bits of our memory addresses So address 14 (1110) maps to cache block 2(10) How to map a memory address

10. How to map a memory address

11. How to find data in the cache

12. Solution

13. Tag + Index

14. The valid bit

15. Cache hit

16. Loading a block into the Cache

17. Spatial Locality

18. Block Addresses

19. Cache mapping

25. Given a cache with 1024 blocks of 4 bytes each, and 32-bit memory addresses, then where would the byte of memory address 6147 be stored? 6147 = 0000 0000 0000 0001 1000 0000 0011 Tag Index block offset Block address in M.M = 1536 Block # 512 in the cache third byte Example Solution 1

26. Given a cache with 1024 blocks of 4 bytes each, and 32-bit memory addresses, then where would the byte of memory address 6147 be stored? Block address in M.M = 6147 / 4 = 1536 Index = 1536 mod 1024 = 512 Block offset = 6147 mod 4 = 3 Example Solution 2

29. Cache Performance If a program uses addresses 2, 6, 2, 6,2,6, …., then each access will result in a cache miss

30. Cache Performance

38. Direct Mapped Cache: Example Ram=128 add Tag Index Byte offset 000 00 00 load 0 load 32 load 0 Index 10 11 00 01 N N N N Valid Tag Data load 24 load 32 Y Y Y Y Y 000 000 010 001 010 Memory[000 00 00] Memory[010 00 00] Memory[010 00 00] Memory[001 10 00] Memory[000 00 00] Byte address Miss: valid 010 00 00 Miss: tag 000 00 00 Miss: tag 001 10 00 Miss: valid 010 00 00 Miss: tag 5/5 Misses

39. 2-Way Set Associative Cache: Example Tag Index Byte offset load 0000 0 00 Index Valid Tag Data 0 N N Y Y Y Y 0100 0100 00000 0011 Memory[0000 0 00] Memory[0011 0 00] Memory[0100 0 00] Memory[0100 0 00] 1 N N Byte address Miss: valid load 0 load 0100 0 00 Miss: tag load 32 load 0000 0 00 Hit! load 0 load 0011 0 00 Miss: tag load 24 load 0100 0 00 Miss: tag load 32 4/5 Misses

40. Fully Associative Cache: Example Tag Index Byte offset load 0000000 Valid Tag Data N N Y Y Y 0000 0100 0110 Memory[00110 00] Memory[00000 00] Memory[01000 00] N N Byte address Miss: valid load 0 load 0100000 Miss load 32 load 0000000 Hit! load 0 load 0011000 Miss load 24 load 01000 00 Hit! load 32 3/5 Misses

41. Performance of Memory System