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Lecture 22

Lecture 22. OUTLINE The MOSFET (cont ’ d) MOSFET scaling Velocity saturation Short channel effects Reading : Pierret 19.1; Hu 7.1, 7.3. MOSFET Scaling. MOSFETs have been steadily miniaturized over time 1970s: ~ 10 m m; today: ~25 nm Benefits:

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Lecture 22

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  1. Lecture 22 OUTLINE The MOSFET (cont’d) • MOSFET scaling • Velocity saturation • Short channel effects Reading: Pierret 19.1; Hu 7.1, 7.3

  2. MOSFET Scaling • MOSFETs have been steadily miniaturized over time • 1970s: ~ 10 mm; today: ~25 nm • Benefits: • Increased device density --> lower cost per function • Improved circuit operating speed • IDsat increases  decreased effective “R” • gate and junction areas decrease decreased load “C” • faster charging/discharging (i.e. td is decreased) EE130/230A Fall 2013 Lecture 22, Slide 2

  3. MOSFET Scaling: Constant-Field Approach • MOSFET dimensions and the operating voltage (VDD) each are scaled by the same factor k>1, so that the electric field remains unchanged. EE130/230A Fall 2013 Lecture 22, Slide 3

  4. Constant-Field Scaling Benefits • Circuit speed improves by k • Power dissipation per function is reduced by k2 EE130/230A Fall 2013 Lecture 22, Slide 4

  5. Since VT cannot be scaled down aggressively, the operating voltage (VDD) has not been scaled down in proportion to the MOSFET channel length: EE130/230A Fall 2013 Lecture 22, Slide 5

  6. MOSFET Scaling: Generalized Approach • Electric field intensity increases by a factor a>1 • Nbody must be scaled up by a to suppress short-channel effects • Reliability and power density are issues EE130/230A Fall 2013 Lecture 22, Slide 6

  7. Velocity Saturation Velocity saturation limits IDsat in sub-micron MOSFETS Simple model: Esat is the electric field at velocity saturation: for e < esat for eesat EE130/230A Fall 2013 Lecture 22, Slide 7

  8. MOSFET I-V with Velocity Saturation In the linear region: EE130/230A Fall 2013 Lecture 22, Slide 8

  9. Drain Saturation Voltage, VDsat • If esatL >> VGS-VT then the MOSFET is considered “long-channel”. This condition can be satisfied when • L is large, or • VGS is close to VT EE130/230A Fall 2013 Lecture 22, Slide 9

  10. Example: Drain Saturation Voltage Question: For VGS = 1.8 V, find VDsat for an NMOSFET with Toxe = 3 nm, VT = 0.25 V, and WT = 45 nm, if L = (a) 10 mm, (b) 1 mm, (c) 0.1 mm (d) 0.05 mm Solution: From VGS , VT and Toxe, meff is 200 cm2V-1s-1. Esat= 2vsat / meff = 8 104 V/cm m = 1 + 3Toxe/WT = 1.2 EE130/230A Fall 2013 Lecture 22, Slide 10

  11. (a) L = 10 mm: VDsat= (1/1.3V + 1/80V)-1 = 1.3 V (b) L = 1 mm: VDsat= (1/1.3V + 1/8V)-1 = 1.1 V (c) L = 0.1 mm: VDsat= (1/1.3V + 1/.8V)-1 = 0.5 V (d) L = 0.05 mm: VDsat= (1/1.3V + 1/.4V)-1 = 0.3 V EE130/230A Fall 2013 Lecture 22, Slide 11

  12. IDsat with Velocity Saturation SubstitutingVDsatfor VDSin the linear-region IDequation gives For very short L: • IDsatis proportional to VGS–VTrather than(VGS– VT)2 • IDsatis not dependent on L EE130/230A Fall 2013 Lecture 22, Slide 12

  13. Short- vs. Long-Channel NMOSFET • Short-channel NMOSFET: • IDsatis proportional to VGS-VTn rather than (VGS-VTn)2 • VDsat is lower than for long-channel MOSFET • Channel-length modulation is apparent EE130/230A Fall 2013 Lecture 22, Slide 13 C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 6-23

  14. Velocity Overshoot • When L is comparable to or less than the mean free path, some of the electrons travel through the channel without experiencing a single scattering event projectile-like motion (“ballistic transport”) • The average velocity of carriers exceeds vsat e.g. 35% for L = 0.12 mm NMOSFET • Effectively, vsat and esat increase when L is very small EE130/230A Fall 2013 Lecture 22, Slide 14

  15. The Short Channel Effect (SCE) R. F. Pierret, Semiconductor Device Fundamentals, Fig. 19.3 • |VT| decreases with L • Effect is exacerbated by high values of |VDS| • This effect is undesirable (i.e. we want to minimize it!) because circuit designers would like VT to be invariant with transistor dimensions and bias condition “VT roll-off” EE130/230A Fall 2013 Lecture 22, Slide 15

  16. Qualitative Explanation of SCE • Before an inversion layer forms beneath the gate, the surface of the Si underneath the gate must be depleted (to a depth WT) • The source & drain pn junctions assist in depleting the Si underneath the gate • Portions of the depletion charge in the channel region are balanced by charge in S/D regions, rather than by charge on the gate • Less gate charge is required to invert the semiconductor surface (i.e. |VT| decreases) EE130/230A Fall 2013 Lecture 22, Slide 16

  17. depletion charge supported by gate (simplified analysis) VG n+ n+ depletion region p The smaller L is, the greater the percentage of depletion charge balanced by the S/D pn junctions: rj Small L: Large L: S D S D Depletion charge supported by S/D Depletion charge supported by S/D EE130/230A Fall 2013 Lecture 22, Slide 17

  18. First-Order Analysis of SCE • The gate supports the depletion charge in the trapezoidal region. This is smaller than the rectangular depletion region underneath the gate, by the factor • This is the factor by which the depletion charge Qdep is reduced from the ideal • One can deduce from simple geometric analysis that WT R. F. Pierret, Semiconductor Device Fundamentals, Fig. 19.4 EE130/230A Fall 2013 Lecture 22, Slide 18

  19. VT Roll-Off: First-Order Model • Minimize DVT by • reducing Toxe • reducing rj • increasing NA • (trade-offs: degraded meff, m) R. F. Pierret, Semiconductor Device Fundamentals, Fig. 19.4 • MOSFET vertical dimensions should be scaled along with horizontal dimensions! EE130/230A Fall 2013 Lecture 22, Slide 19

  20. Drain Induced Barrier Lowering (DIBL) • As the source and drain get closer, they become electrostatically coupled, so that the drain bias can affect the potential barrier to carrier diffusion at the source junction.  VT decreases (i.e. OFF state leakage current increases) C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 7-5 EE130/230A Fall 2013 Lecture 22, Slide 20

  21. Punchthrough • A large drain bias can cause the drain-junction depletion region to merge with the source-junction depletion region, forming a sub-surface path for current conduction. • IDsat increases rapidly with VDS • This can be mitigated by doping the semiconductor more heavily in the sub-surface region, i.e. using a “retrograde” doping profile. R. F. Pierret, Semiconductor Device Fundamentals, Fig. 19.6 EE130/230A Fall 2013 Lecture 22, Slide 21

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