PIDS Summary Dec 9, 2008 Seoul, Korea

1. PIDS SummaryDec 9, 2008Seoul, Korea Kwok Ng SRC/USARich Liu Macronix/TaiwanHidekazu Oda Renesas/Japan Hirofumi Inoue Toshiba/JapanMakoto Yoshimi Soitec/JapanSeon-Yong Cha Hynix/KoreaGyoyoung Jin Samsung/KoreaWons Yang Samsung/KoreaKeeHoon Lee IPS/Korea

2. Japan: Oda, Hidekazu Inoue, Hirofumi Akasaka, Yasushi Eimori, Takahisa Hiramoto, Toshiro Hori, Atsushi Ida, Jiro Imai, Kiyotaka Kasai, Naoki Mifuji, Michihiko Ogura, Mototsugu Sawada, Shizuo Shibahara, Kentaro Sugii, Toshihiro Tadaki, Yoshitaka Tagawa, Yukio Takagi, Shinnichi Tanaka, Tetsu Yoshimi, Makoto Europe: Skotnicki, Thomas Boeuf, Frederic DeMeyer, Kristin Jurczak, Malgorzata Lander, Robert Poiroux, Thierry Schulz, Thomas Taiwan: Liu, Rich Ma, Mike Diaz, Carlos See, Yee-Chaung Korea: Cha, SeonYong Jin, Gyoyoung U.S: Ng, Kwok Antoniadis, Dimitri Brewer, Joe E. Chang, Chorng-Ping Cheung, Charles Dellin, Theodore A Hutchby, Jim Maszara, Witek Ning, Tak H. Prall, Kirk Tsai, Wilman Wu, Jeff Xiang, Qi Yeap, Geoffrey Yu, Scott Zeitzoff, Peter M.

3. Outline • PIDS Scope and Sub-Categories • 2008 Update Summary • On-Going Activities • 2009 Goals

4. PIDS = Process Integration, Devices, and Structures • Scopes: • Provide physical and electrical requirements and solutions for sustaining IC performance scaling (performance = speed, density, power, functionality…) • On logic and memory devices: • Structures • Process-integration issues • Reliability

5. PIDS Sub-Categories • Logic • HP = High Performance (mP…) • LOP = Low Operating Power (notebook…) • LSTP = Low Standby Power (cellular…) • Memory • Nonvolatile • DRAM • Reliability

6. 2008 Update: Background • Japan PIDS team provided survey on Lg (physical gate lengths) for HP, LSTP, and LOP logic devices, along with reverse-engineering data from FEP, helped to establish new slowed-down scaling model. • 2008 update adopts new Lg rules proposed by ORTC.

7. 2008 Update: Logic • HP and LOP devices using new Lg rules.LSTP devices remain same. • Data entries are based on “interpolation” of 2007 data.First 3 years are re-calculated by MASTAR. • Some “bumps” in first ~3 years, due to merging of 2005 & 2007 tables. • UTB-FD and DG follow delay of Lg rules.

8. 2008 Update: DRAM • No change. • Inconsistency in 2007 tables between ORTC & PIDS pointed out and explained. To be fixed in 2009. • PIDS table: • Lg values using 2nd-best figures among 5 companies in DRAM survey. • Lg follows 2.5-yr cycle 2007–2009, and 3-yr cycle 2009–2022. • Cell size calculated with HP numbers in table. • ORTC table: • Lg follows 3-yr cycle 2007–2022. • Cell size calculated with rounded HP number.

9. 2008 Update: Nonvolatile Memory • No change in 2008 update, for both NAND flash & NOR flash scaling.

10. PIDS Scope and Sub-Categories • 2008 Update Summary • On-Going Activities • 2009 Goals

11. On-Going Activities on Logic • Propose/consider new speed metric using ring oscillator or inverter. • Propose/consider providing equations to derive such speed, in addition to MASTAR. • Reconsider scaling parameters (gate fringing factor, S/D series resistance…) • Speed scaling slower than 17%/year. • Updating MASTAR. • Variability as a factor in scaling (Europe PIDS).

12. On-Going Activities on Memory • Survey on DRAM presented by Japan PIDS team. • Nonvolatile memory survey in progress. Will be presented in Spring meeting, 2009.

13. 2009 Goals • MASTAR calculation on CV/I to replace values obtained from interpolation in 2008 tables. • Consider new speed metric using ring oscillator or inverter. • Consider equations to derive new speed metric above, in addition to MASTAR. • Incorporate new speed scaling factor smaller than 17%/year.

14. 2009 Goals (cont’d) • Variability as a factor in scaling. • Adjustment of DRAM and nonvolatile memory scaling, pending on survey results.