1. Muon Tracker Front-end Electronics PHENIX FEE Review June 10-11, 1998 Brookhaven National Laboratory Belinda Wong-Swanson LANL NIS-4 Tel: 505-665-8787 Email: bwong-swanson@lanl.gov

2. Topics • MuTr Signal Requirements and Channel Counts • MuTrFEE Design Team • MuTrFEE Overview • Technical Design Requirement & Constraints • Detector-FEE Circuit Requirements & Constraints • Cathodes FEM Layout & “FEM” Description • Cathode FEE Counts

3. Topics (continued) • Current Status • Prototype Plan and Schedule • MuTrFEE Schedule • Overall Schedule • Fabrication Schedule • Major Milestones

4. MuTr Signal Requirements • Cathodes • 4 pulse-height samples per event (stale hits rejection) • Channel Matching ~ 1% (after calibration) • Noise < 3000 e¯ • 11-bit dynamic range (0.1  10 x 80 fC) • ~750ns integration time & < 12s decay time for 10 –150 pF strip capacitances

5. MuTr Signal Requirements • Anodes • Latch (1-bit A/D) • 10 – 50 pF input capacitance, ~70 ns chg collect’n time • DO NOT IMPACT ACCEPTANCE • Must hide in shadows of detector octant frames

6. MuTr Channel Counts

7. MuTrFEE Team *Grad Students have grants  Free to PHENIX

8. MuTrFEE Technical Design Requirements & Constraints • General • Interface to PHENIX Online System • Provide Ancillary (Remote) Controls & Monitors • Robustness (No access for ~months at a time) • Nothing between Stations 1 & 2 • Station-1 electonics upstream of Station-1 detectors • Stations-2&3 electronics between Stations-2&3 detectors

9. MuTrFEE Technical Design Requirements & Constraints (cont’d.) • Stations-2&3 electronics inside magnet • minimal-to-no access for very long periods • engineer against multiple single-point failures • low-noise electronics in a magnetic field • no (iron-core) transformers • no electric motors/fans • low-noise electronics inside a dirty “oven” - 30°C ambient • cooling in a hot/humid/stagnant environment • fluid-based cooling • dried atmosphere with good thermal conduction • enclosures for environmental isolation

10. MuTrFEE Technical Design Requirements & Constraints (cont’d.) • Nothing in acceptance downstream of Sta-1 • Extremely limited “radial” space at Station-2 • Anodes readout must hide behind Sta-2 octant framesand not enlarge “dead bands” at Sta-3 octant boundaries • Clear lines of sight for alignment monitoring • Limited space in all dimensions for cathodes readout at Stations 2&3 • Anodes readout must have radial “holes” along spokes

13. MuTrFEE Technical Design Requirements & Constraints (cont’d.) • Limited space in both r and z at Station-1 • Also must leave space for BB-counters’ cabling • Minimal cathode analogue-cable lengths • avoid noise pickup • Limited magnet “penentrations” availablefor MuTrEE services and signals • Lower ones consumed by magnet power & cooling • Must not distort or load detector structures

14. Top view of an octant between Station 2 and Station 3, South-Arm

15. MuTrFEE Technical Design Requirements & Constraints (cont’d.) • Top 5 lampshade panels are removable • Cannot attach to/mount anything from them • Must try to avoid having anything delicate near them • Big, heavy, oddly shaped, unstable orientations • Can’t rely solely on jigs & rigging fixtures • Must avoid noise sources safely • Humidity + dissimilar metals  cathodic currents • Need electrical isolation wrt det mounts & magnet • BUT must not allow hazardous step potentials to develop

16. Detector-FEE Circuit Requirements and Constraints • Detectors + FEE constitute a LARGE, DISTRIBUTED, REACTIVE NETWORK • Difficult to establish a “True” Ground • Cathode and Anode electrodes are physically far apart • Ground & Power Paths are Intimately Connected to Detector & FEE Operations • Signal Returns are tied to Preamp LV Power Rails

17. Detector-FEE Circuit Requirements and Constraints (continued) • Grounding & Power Distribution must be designed to minimize noise and EMI pickup • Especially for Cathodes subsystem • Grounding & Power Distribution must be designed to protect equipment & personnel

18. Detector-FEE Power and Grounding Strategies • Independent returns for all signals to only one common at the detectors • Dedicated plane in detector PCBs • Isolation of detector frames from magnet to avoid long term degradation of grounds due to corrosion with dissimilar metals • Low voltage DC power “floated” with respect to (HV + detectors)

19. Detector-FEE Power and Grounding Strategies (continued) • Passive ground isolation and filtering in both HV and LV circuits to prevent pickup on power cables from leaking into detector-FEE circuits • Isolation of FEE frames from detector frames and magnets and mechanical structures. • Bleeder resistors in HV distribution to allow the detector to discharge in case of HV faults.

20. Detector-FEE Power and Grounding Strategies (continued) • Considering active monitoring for ground faults between magnets, detectors, and FEE structures that may lead to step-potentials build-up during abnormal operations or failures. • Studying details regarding filtering, TVSS, etc. in AC-power system.

21. ARCNet T&FC LVDC DCM Ancillary Controls & Monitors C A I C A C A I C B C R O C B C R O C A S C I D A Q I F P C BACKPLANE Cathodes FTM Cathode Detector Signals: 64 Strips/CROC, 4 Samples/Strip/Event; 128 Strips/FEM==>512 Data words/40usec readout Cathodes FEM Layout

22. Definition of MuTr “FEM” • Chassis has 2 Front End Modules (FEMs) • Half-chassis has 1 FEM • FEM has • Backplane • Mates with FEM Transition Module • Analogue/Digital interconnect for Cathodes/Anodes

23. Definition of MuTr “FEM” (continued) • Readout Interfaces (2) • Slow Controls Interface • ARCNet + Serial for configuration & initialization • DAQ Interface • Glink-in + Fast Timing & Control + Data Formatter + GLink-out • sometimes called “Heap Manager” in other subsystems

24. Definition of MuTr “FEM” (continued) • ReadOut Cards • Cathodes ROC (2) • pre-amp + AMU-ADC + some buffering • Analogue ins via Cathodes Analogue Input & Calibration Card • So can replace FEM cards w/o disturbing detector cables • Analogue inputs perpedicular to fast backplane signals • Includes circuitry for precision cathodes calibration

25. SD_OUT1 Vr CAIC DATA CLOCK DATA CLOCK From Det. VREF ANALOG OUT NO DATA CLOCK RD_WR* RD_WR* LATCH V RD_WR* LATCH 8-BIT DAC1 NC CH1 SD_OUT1 Preamp ASIC 1 of 8 LATCH Ccal SD_OUT2 DAC1_8BIT From Det. SD_OUT SD_OUT3 RST A1 SD_OUT4 (FROM SLOW CONTROLS) EN A0 SUBSEL2 EN CH2 A1 SUBSEL1 A0 SWITCH CONTROL Ccal SUBSEL0 From Det. EN SWITCH EN1 CONTROL LOGIC CRD_SEL SD_OUT2 Vr DAC1_8BIT DAC2_8BIT VREF CH3 ANALOG OUT NO Ccal DAC3_8BIT DATA CLOCK SD_IN From Det. DAC4_8BIT V RD_WR* 8-BIT DAC2 NC LATCH SWITCH_EN1 DAC2_8BIT CH4 SWITCH_EN2 RST Ccal SWITCH_EN3 A1 EN From Det. A0 BACKPLANE SWITCH_EN4 EN SWITCH CONTROL SWITCH EN2 CH5 SD_OUT3 Ccal Vr MB0 (RESET) From Det. RST MB1 (RESET) VREF ANALOG OUT NO DATA CLOCK MB6 (CAL) CH6 (INJECT) V RD_WR* 8-BIT DAC3 CONTROL LOGIC MB7 (CAL) NC Ccal (FROM TIMING & FAST CONTROLS) LATCH From Det. DAC3_8BIT MODE_ENBL RST BEAM CLOCK A1 EN CH7 A0 EN Ccal From Det. SWITCH CONTROL SWITCH EN3 SD_OUT3 Vr CH8 VREF Ccal ANALOG OUT NO DATA CLOCK V RD_WR* 8-BIT DAC4 NC To 14 channels To 14 channels LATCH CROC CRDSEL DAC4_8BIT RST To 14 channels CRDSEL2 A1 To 14 channels EN HARDWIRED CARD SELECT and CONTROL LOGIC A0 (FROM SC) CRDSEL1 EN CRDSEL0 SWITCH CONTROL SWITCH EN4

26. 8 channel pre-amp 11-bits of data Readout control AMU-ADC 8 channel pre-amp Full scale count Control 8 channel pre-amp Read address Write address 8 channel pre-amp 8 channel pre-amp AMU-ADC 8 channel pre-amp 8 channel pre-amp 11-bits of data 8 channel pre-amp ARCNet Timing & fast controls CROC Block Diagram From cathode analog input and calibration card MuTrFEE has only 2 ASICs: CPA which is unique to MuTr, and AMUADC which is common to 4 PHENIX subsystems

27. Cathode FEE Counts

28. Current Status • CPA prototype chips now under test • 2 test stands, allow both bench-top and on-detector tests • Bench-top test results all agree with expectations from simulations • 2 minor design mods & no additional prototyping req’d in order for all design specs to be met • Foresee no obstacles to completion by Jul98 • Additional tests will focus on analog interconnects and CAIC-circuit prototyping • Ready for CPA Production ASAP after 10/1/98

29. Current Status (continued) • Backplane design (including layout and simulation) almost complete (on hold for final decisions regarding proposed simplifications) • Detailed CFTM and CAIC design underway • Detailing AMUADC timing and control requirements (to accommodate 4 samples/event) underway • Preparing for on-detector tests with CPA test stand

30. Current Status (continued) • Beginning to develop test equipment for prototype testing of FEM boards • Completed FEM Chassis design • Detailing cooling system design • Detailing cabling and services plants routing requirements • Detailing mechanics designs • Beginning to develop installation scenarios.

31. Cathode Prototype Plan and Schedule • Plan presented at May98 Muon Arms MiniTAC Review was to delay almost all prototyping until 10/1/98. LANL P-Division has agreed to provide some support for earlier prototyping. • Plan explicitly incorporates 2 rounds of prototyping. • Prototyping and integrated-FEM tests to be completed by June 99.

32. MuTrFEE Schedule (Calendar in Fiscal Year)

33. Fabrication & Integration Milestones • 10/01/98 CPA ASIC production • 06/17/99 Cathodes FEM design integration and tests completed • Start fab’ing prod’n parts for S-Arm cathodes • After 04/01/99 (JFY boundary) • 05/99-09/99 Prepare cathodes FEM test stations • 08/05/99 Begin FEE infrastructure installation • after detector installation complete

34. Fabrication & Integration Milestones (continued) • 09/99-01/00 Assemble and test S-Arm cathodes FEM • 11/10/99 Begin S-Arm cathodes FEM installation in assembly area • 02/14/00 S-Arm cathodes FEMs installed • S-Arm ready for roll-in

35. Major Milestones After S-Arm Installation • In current project plan • 03/01 N-Arm cathodes FEMs installed • 07/01 S-Arm anodes FEMs installed • 08/01 N-Arm anodes FEMs installed • These dates are dependent on • access to collision hall • availability of AEE contingency funds for anodes development and production