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Chapter 4. Modular Combinational Logic. Decoders. Decoders. n to 2 n decoder n inputs 2 n outputs For each input, one and only one output will be active. Uses: “Minterm generator” Wordline (memory) circuit Code conversion Routing data. 2 to 4 Decoder Example.

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chapter 4

Chapter 4

Modular Combinational Logic

decoders3
Decoders
  • n to 2n decoder
    • n inputs
    • 2n outputs
  • For each input, one and only one output will be active.
  • Uses:
    • “Minterm generator”
    • Wordline (memory) circuit
    • Code conversion
    • Routing data
example
Example
  • Using only a 3x8 decoder and two-input OR gates, design a logic circuit which implements the following Boolean equation
solution
Solution

m2

m4

m5

2x4 decoder with enable
2x4 Decoder with Enable
  • Enable is abbreviated as EN
  • EN is called a Control Signal
  • Control Signals can be
    • Active High Signal
      • EN = 1 – Turns “ON” Decoder
    • Active Low Signal
      • EN=0 – Turns “ON” Decoder
2 x 4 decoder with active high enable truth table short hand notation
2 x 4 Decoder with Active High Enable – Truth Table (Short hand notation)

d = don’t care

En has “highest” priority.

If En=0, we “don’t care” about x1 or x0 because Y=0

2 x 4 decoder with active low enable truth table short hand notation
2 x 4 Decoder with Active Low Enable – Truth Table (Short hand notation)

d = don’t care

En has “highest” priority.

If En=1, we “don’t care” about x1 or x0 because Y=0

example27
Example
  • Design a 3x8 decoder using only 2x4 decoders and NOT gates.
solution28
Solution

“On” when A=0

“On” when A=1

encoders31
Encoders
  • Opposite of a decoder
  • 2n to n encoder
    • 2n inputs
    • n outputs
  • For each input, the circuit will produce an “encoded” output
example 4 to 2 binary encoder truth table
Example: 4to 2 Binary EncoderTruth Table

Assume only one input high at a time!!

problems with initial design
Problems with initial design
  • Q: How do we tell the difference between an input of all 0’s (i.e. X=0) and X=1?
  • A: Add another output (IA) that indicates that the input is valid. Let’s make IA active low.
problems with initial design35
Problems with initial design

If IA = 1 => all lines are 0

If IA = 0 => at least one line is 1

  • Q: What happens if more than one input is high at the same time?
  • A: Design a “priority” encoder that will encode the input with the highest priority.
  • Let’s set X3 with the highest priority, followed by X2, X1, and X0
solution37
Solution

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Y1

Y0

multiplexer data selectors

Multiplexer/Data Selectors

MUX

Very Important Module!!!

multiplexer mux data selector
Multiplexer(MUX)/Data Selector
  • N to 1 multiplexer
    • n data input lines
    • Log2(n) control inputs
    • One output
  • This circuit will “connect” the selected input to the output. The selected input is specified by a decoding of the control inputs.
example 4 to 1 mux truth table
Example: 4to 1 MUX Truth Table

Control

Inputs

Output

Data Inputs

d = don’t care / Di = data on input i

4 to 1 mux equation
4 to 1 MUX Equation

D’s are the DATA inputs, AB are control inputs and called

the “select” lines.

4 to 1 mux circuit
4 to 1 MUX Circuit

Control Inputs

Data Inputs

Output

2x4 Decoder

Only a single AND gate will

be “ON” at a time.

4 to 1 mux symbol
4 to 1 MUX Symbol

Data

Inputs

Output

Control

Inputs

data and control paths
Data and Control Paths

Control Path

Outputs

Logic

Data Path

Inputs

Data Path

Outputs

Control Path

Inputs

example47
Example
  • Using a 4x1 MUX, design a logic circuit which implements:

We have,

Y

example48
Example
  • Using a 4x1 MUX, design a logic circuit which implements:
multi bit multiplexers
Multi-bit Multiplexers
  • J-bit nx1 mux

d0

d1

J bits

deep

d2

J bits

deep

F

dn-1

sel

log2n

j=0 to 3

This is just J separate nx1 multiplexers

example 4 bit 4x1 mux
Example 4-bit 4x1 MUX

D0[3..0]

D0[3..0]

D1[3..0]

D1[3..0]

F[3..0]

D2[3..0]

F[3..0]

4 bits deep

D2[3..0]

D3[3..0]

D3[3..0]

A B

A

B

j=0 to 3

This is just 4 separate 4x1 muxes

example53
Example
  • 4-bit 4x1 MUX

Bit 0

Bit 1

Bit 2

Bit 3

example 4 bit 4x1 mux54
Example 4 bit 4x1 MUX
  • For the jth output, we have

D0[j]

D1[j]

F[j]

D2[j]

D3[j]

A

B

example 4 bit 4x1 mux55
Example 4 bit 4x1 MUX
  • For the bit 0 output, we have

D0[0]

D1[0]

F[0]

D2[0]

D3[0]

A

B

example 4 bit 4x1 mux56
Example 4 bit 4x1 MUX
  • For the bit 1 output, we have

D0[1]

D1[1]

F[1]

D2[1]

D3[1]

A

B

example 4 bit 4x1 mux57
Example 4 bit 4x1 MUX
  • For the bit 2 output, we have

D0[2]

D1[2]

F[2]

D2[2]

D3[2]

A

B

example 4 bit 4x1 mux58
Example 4 bit 4x1 MUX
  • For the bit 3 output, we have

D0[3]

D1[3]

F[3]

D2[3]

D3[3]

A

B

example 4 bit 4x1 mux59
Example 4 bit 4x1 Mux

Complete Circuit

Bit 0

F[0]

Bit 1

F[1]

F[2]

Bit 2

F[3]

Bit 3

design example61
Design Example
  • Using a 4bit 4x1 MUX, design a 8bit

4x1 MUX

demultiplexer data distributor
Demultiplexer/Data Distributor
  • Opposite of a multiplexer
  • 1 to N demultiplexer
    • 1 data input
    • N data outputs
    • Log2(n) control inputs
  • This circuit will “connect” a data input to one and only one output. The selected output is specified by a decoding of the control inputs.
example 1 to 4 demux truth table
Example: 1to 4 DeMUX Truth Table

d = don’t care / Di = data on input i

1 to 4 demux equations
1 to 4 DeMUX Equations

D is the DATA inputs, AB are control inputs and called

the “select” lines.

1 to 4 demux circuit
1 to 4 DEMUX Circuit

Only one

F will be

active

2x4 Decoder

Only 1 AND gate will

be “ON”

1 to 4 demux symbol
1 to 4 DEMUX Symbol

Selected

Lines

Outputs

Data

Input

example69
Example
  • Design a 3x8 decoder using only 2x4 decoders and NOT gates.
solution70
Solution

“On” when A=0

“On” when A=1

half adder truth table
Half Adder-Truth Table
  • S=A+B (arithmetic sum)
full adder truth table
Full Adder-Truth Table
  • S=A+B+C (arithmetic sum)
full adder
Full Adder

You can show!!!

synthesis
Synthesis

Logic Equation

Logic Circuit

synthesis78
Synthesis

Logic Equation

Logic Circuit

synthesis full adder circuit
Synthesis Full Adder Circuit

A

B

S(0)

C

S(1)

S(0)

S(1)

Simulation

verification
Verification

We verify the circuit via a simulation

Logic Simulation

Inputs

S(0)

S(1)

S 00 01 01 10 01 01 01 11

Outputs

verification summary
Verification Summary

A

B

S(0)

C

S(1)

Circuit

S(0)

S(1)

Simulation

documentation

FullAdder

A

S(1)

B

S(0)

C

Documentation

A

B

S(0)

C

S(1)

Block Diagram

conceptualization
Conceptualization
  • 4-bit adder (worst case)

1

1

1

1111

1111

11110

For the “worst case” we need to add

three bits to generate a single output bit

with a possible carry out.

Can we use our single bit adder for this?

ripple carry adder85
Ripple Carry Adder
  • We can cascade several full adders to create a ripple carry adder
  • The circuit gets its name because the carry bit “ripples” from one bit position to the next
conceptualization86

FullAdder

FullAdder

A

A

S(1)

S(1)

B

B

S(0)

S(0)

C

C

Conceptualization

First, let’s look at two bits

A(1)

B(1)

Sum(1)

A(0)

B(0)

Sum(0)

What about the carry?

conceptualization87

FullAdder

FullAdder

A

A

S(1)

S(1)

B

B

S(0)

S(0)

C

C

Conceptualization

Let’s connect the two full adders

A(1)

B(1)

S(1)

Cin

Cout

A(0)

B(0)

S(0)

0

Set carry in for first bit to 0. Why?

analysis

0

0

00

00

0

0

000

FullAdder

FullAdder

0

A

A

S(1)

S(1)

0

0

B

B

S(0)

S(0)

C

C

Analysis

Let’s test this for a few cases:

0

0

0

Correct!!!

Rule of thumb: Always test simple cases first!!

analysis89

1

1

11

11

1

1

110

FullAdder

FullAdder

1

A

A

S(1)

S(1)

0

0

B

B

S(0)

S(0)

C

C

Analysis

Let’s test this for the a few cases

1

1

1

Correct!!!

analysis90

01

01

010

FullAdder

FullAdder

A

A

S(1)

S(1)

B

B

S(0)

S(0)

C

C

Analysis

Let’s test this for the a few cases

0

0

0

1

1

1

1

1

0

0

Correct!!!

8 bit ripple carry adder
8-bit Ripple Carry Adder
  • Use two 4-bit adders
16 bit ripple carry adder
16-bit Ripple Carry Adder
  • Use two 8-bit adders
subtraction circuit96
Subtraction Circuit
  • Calculate 2’s complement of B
  • Add –B to A
function table for add sub module
Function Table for Add/Sub Module

Add is a control input. It is active low. This means that the module will compute A+B when Add=0. It will compute A-B when Add=1.

add sub circuit100

Add/Sub Circuit

Design using Modules

add sub circuit102
Add/Sub Circuit

Add operation. Add=0

0

0

add sub circuit103
Add/Sub Circuit

Sub operation. Add=1

1

1

numerical overflow underflow
Numerical Overflow/Underflow
  • 2’s complement number
    • We have S=A+B
  • Range of sum
  • Overflow occurs if
  • Underflow occurs if
example overflow
Example: Overflow
  • Let n=4, Range is
  • Let A=$7, B=$7, then S=$7+$7=$E, but $E=%1110 = -2, so Overflow has occurred.
example overflow108
Example: Overflow
  • Let’s examine this more closely

-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7

+7

8,9,A,B,C,D,E,F,0,1,2,3,4,5,6,7

So, overflow is the same as “wrap around.”

example underflow
Example: Underflow
  • Let n=4, let A=-7 and B=-7,
  • in 2’s complement, A=B=$9, S=$9+$9=$12=$02
  • so underflow has occurred.
example underflow110
Example: Underflow
  • Let’s examine this more closely

-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7

+1

+6

So, underflow is the same as “wrap around.”

overflow underflow detection111
Overflow/Underflow Detection
  • How do we detect overflow and underflow?
    • First adding a positive to a negative number is always OK.
      • 4 bit example: 7 + (-8) = -1
    • Let’s examine the sum of the MSB’s to determine overflow and underflow.
      • Set V=1, if overflow/underflow occurs
examination of msb
Examination of MSB

a,b are the MSBs of A and B. cin is carry in; cout=carry out

overflow underflow detection114
Overflow/Underflow Detection
  • You can also use
  • That is, if for the MSB carry_in is not equal to carry_out, overflow or underflow has occurred.
equal comparator
Equal Comparator
  • Design a logic circuit which will compute

F0 = (A = B)

solution120
Solution

You can show,

not equal comparator
Not Equal Comparator
  • Design a logic circuit which will compute

F = (A <> B)

F = (A = B)

i.e. Just invert our Equal Comparator circuit

magnitude comparator
Magnitude Comparator
  • Design a logic circuit which will compute

F2 = (A>B)

F1 = (A<B)

Let’s develop a truth table for 2-bits

arithmetic logic unit alu
Arithmetic Logic Unit (ALU)

A,B are data inputs of n bits each in depth

S is a control input. We have 2m operations

F is the output

example130
Example
  • Let n=4,m=3
  • We have A[3..0] and B[3..0]
  • With m=3, we have 23 = 8 operations
  • Let’s look at a possible function table
design using a truth table
Design using a Truth Table
  • How large is the truth table?
    • 2n from data inputs A and B
      • Example: n=8, we have 16 data inputs
      • A[7..0] and B[7..0]
    • 3 control inputs
    • Total of 2n+3 inputs
      • N=8, we have 19 inputs
    • Our truth table will have
    • 192 (361) rows and 8 outputs
  • Too complex. Let’s explore another alternative using a “system” or modular approach
design using modules
Design using Modules
  • Note:
    • For S2=0, we have logic operations
    • For S2=1, we have arithmetic operations
    • So, let’s use S2 to control a 2x1 MUX
    • to select between logic and arithmetic operations, so our top level design would look like:
alu design s2 0
ALU Design S2=0

With S2=0, F is the output from

the logic module

alu design s2 1
ALU Design S2=1

With S2=1, F is the output from

the arithmetic module

function table for logic module
Function Table for Logic Module
  • S2=0

We can use a 4x1 mux to

implement this module

logic module design140
Logic Module Design

F=AB

AND Operation

S[1..0]=00

0 0

logic module design141
Logic Module Design

F=A+B

OR Operation

S[1..0]=01

0 1

logic module design142
Logic Module Design

F=A

NOT Operation

S[1..0]=10

1 0

logic module design143
Logic Module Design

F=A XOR B

XOR Operation

S[1..0]=11

1 1

arithmetic module

Arithmetic Module

Let’s use our ADD/SUB Module

function table for arithmetic ops
Function Table for Arithmetic Ops

Note:

S0 can be use to indicate Addition or Subtraction.

S1 can be use to indicate the B data input

arithmetic module design153

A

S

B

Arithmetic Module Design

F=A+B

S[1..0]=00

0

0

arithmetic module design154

A

S

B

Arithmetic Module Design

F=A-B

S[1..0]=01

1

0

arithmetic module design155

A

S

B

Arithmetic Module Design

F=A+1

S[1..0]=10

0

1

arithmetic module design156

A

S

B

Arithmetic Module Design

F=A-1

S[1..0]=11

1

1

total design
Total Design

Logic Module

Arithmetic Module