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### Chapter 4

### Basic Arithmetic Elements

### Add/Sub Circuit

### TPS Quiz

### TPS Quiz

### TPS Quiz

### Arithmetic Module

### Overall Design

Modular Combinational Logic

Decoders

- n to 2n decoder
- n inputs
- 2n outputs
- For each input, one and only one output will be active.
- Uses:
- “Minterm generator”
- Wordline (memory) circuit
- Code conversion
- Routing data

2 to 4 Decoder – Truth Table

- 2 to 4 decoder

Example

- Using only a 3x8 decoder and two-input OR gates, design a logic circuit which implements the following Boolean equation

2x4 Decoder with Enable

- Enable is abbreviated as EN
- EN is called a Control Signal
- Control Signals can be
- Active High Signal
- EN = 1 – Turns “ON” Decoder
- Active Low Signal
- EN=0 – Turns “ON” Decoder

2 x 4 Decoder with Active High Enable – Truth Table (Short hand notation)

d = don’t care

En has “highest” priority.

If En=0, we “don’t care” about x1 or x0 because Y=0

2 x 4 Decoder with Active Low Enable – Truth Table (Short hand notation)

d = don’t care

En has “highest” priority.

If En=1, we “don’t care” about x1 or x0 because Y=0

Example

- Design a 3x8 decoder using only 2x4 decoders and NOT gates.

Encoders

- Opposite of a decoder
- 2n to n encoder
- 2n inputs
- n outputs
- For each input, the circuit will produce an “encoded” output

Example: 4to 2 Binary EncoderTruth Table

Assume only one input high at a time!!

Problems with initial design

- Q: How do we tell the difference between an input of all 0’s (i.e. X=0) and X=1?
- A: Add another output (IA) that indicates that the input is valid. Let’s make IA active low.

Problems with initial design

If IA = 1 => all lines are 0

If IA = 0 => at least one line is 1

- Q: What happens if more than one input is high at the same time?
- A: Design a “priority” encoder that will encode the input with the highest priority.
- Let’s set X3 with the highest priority, followed by X2, X1, and X0

Multiplexer(MUX)/Data Selector

- N to 1 multiplexer
- n data input lines
- Log2(n) control inputs
- One output
- This circuit will “connect” the selected input to the output. The selected input is specified by a decoding of the control inputs.

4 to 1 MUX Circuit

Control Inputs

Data Inputs

Output

2x4 Decoder

Only a single AND gate will

be “ON” at a time.

Example

- Using a 4x1 MUX, design a logic circuit which implements:

Multi-bit Multiplexers

- J-bit nx1 mux

d0

d1

J bits

deep

d2

J bits

deep

F

…

dn-1

sel

log2n

j=0 to 3

This is just J separate nx1 multiplexers

Example 4-bit 4x1 MUX

D0[3..0]

D0[3..0]

D1[3..0]

D1[3..0]

F[3..0]

D2[3..0]

F[3..0]

4 bits deep

D2[3..0]

D3[3..0]

D3[3..0]

A B

A

B

j=0 to 3

This is just 4 separate 4x1 muxes

Example 4 bit 4x1 MUX

- Symbol

Demultiplexer/Data Distributor

- Opposite of a multiplexer
- 1 to N demultiplexer
- 1 data input
- N data outputs
- Log2(n) control inputs
- This circuit will “connect” a data input to one and only one output. The selected output is specified by a decoding of the control inputs.

Example: 1to 4 DeMUX Truth Table

d = don’t care / Di = data on input i

Example

- Design a 3x8 decoder using only 2x4 decoders and NOT gates.

Half Adder

Half Adder-Truth Table

- S=A+B (arithmetic sum)

Full Adder-Truth Table

- S=A+B+C (arithmetic sum)

Full Adder

You can show!!!

Verification

We verify the circuit via a simulation

Logic Simulation

Inputs

S(0)

S(1)

S 00 01 01 10 01 01 01 11

Outputs

Conceptualization

- 4-bit adder (worst case)

1

1

1

1111

1111

11110

For the “worst case” we need to add

three bits to generate a single output bit

with a possible carry out.

Can we use our single bit adder for this?

Ripple Carry Adder

- We can cascade several full adders to create a ripple carry adder
- The circuit gets its name because the carry bit “ripples” from one bit position to the next

FullAdder

A

A

S(1)

S(1)

B

B

S(0)

S(0)

C

C

ConceptualizationFirst, let’s look at two bits

A(1)

B(1)

Sum(1)

A(0)

B(0)

Sum(0)

What about the carry?

FullAdder

A

A

S(1)

S(1)

B

B

S(0)

S(0)

C

C

ConceptualizationLet’s connect the two full adders

A(1)

B(1)

S(1)

Cin

Cout

A(0)

B(0)

S(0)

0

Set carry in for first bit to 0. Why?

8-bit Ripple Carry Adder

- Use two 4-bit adders

16-bit Ripple Carry Adder

- Use two 8-bit adders

Subtraction Circuit

- Calculate 2’s complement of B
- Add –B to A

Function Table for Add/Sub Module

Add is a control input. It is active low. This means that the module will compute A+B when Add=0. It will compute A-B when Add=1.

Design using Modules

17-18

Numerical Overflow/Underflow

- 2’s complement number
- We have S=A+B
- Range of sum
- Overflow occurs if
- Underflow occurs if

Example: Overflow

- Let n=4, Range is
- Let A=$7, B=$7, then S=$7+$7=$E, but $E=%1110 = -2, so Overflow has occurred.

Example: Overflow

- Let’s examine this more closely

-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7

+7

8,9,A,B,C,D,E,F,0,1,2,3,4,5,6,7

So, overflow is the same as “wrap around.”

Example: Underflow

- Let n=4, let A=-7 and B=-7,
- in 2’s complement, A=B=$9, S=$9+$9=$12=$02
- so underflow has occurred.

Example: Underflow

- Let’s examine this more closely

-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7

+1

+6

So, underflow is the same as “wrap around.”

Overflow/Underflow Detection

- How do we detect overflow and underflow?
- First adding a positive to a negative number is always OK.
- 4 bit example: 7 + (-8) = -1
- Let’s examine the sum of the MSB’s to determine overflow and underflow.
- Set V=1, if overflow/underflow occurs

Examination of MSB

a,b are the MSBs of A and B. cin is carry in; cout=carry out

Overflow/Underflow Detection

- We find

Overflow/Underflow Detection

- You can also use
- That is, if for the MSB carry_in is not equal to carry_out, overflow or underflow has occurred.

19-20

Solution

You can show,

Not Equal Comparator

- Design a logic circuit which will compute

F = (A <> B)

F = (A = B)

i.e. Just invert our Equal Comparator circuit

Magnitude Comparator

- Design a logic circuit which will compute

F2 = (A>B)

F1 = (A<B)

Let’s develop a truth table for 2-bits

21

Arithmetic Logic Unit (ALU)

A,B are data inputs of n bits each in depth

S is a control input. We have 2m operations

F is the output

Example

- Let n=4,m=3
- We have A[3..0] and B[3..0]
- With m=3, we have 23 = 8 operations
- Let’s look at a possible function table

Design using a Truth Table

- How large is the truth table?
- 2n from data inputs A and B
- Example: n=8, we have 16 data inputs
- A[7..0] and B[7..0]
- 3 control inputs
- Total of 2n+3 inputs
- N=8, we have 19 inputs
- Our truth table will have
- 192 (361) rows and 8 outputs
- Too complex. Let’s explore another alternative using a “system” or modular approach

Design using Modules

- Note:
- For S2=0, we have logic operations
- For S2=1, we have arithmetic operations
- So, let’s use S2 to control a 2x1 MUX
- to select between logic and arithmetic operations, so our top level design would look like:

Let’s use our ADD/SUB Module

Function Table for Arithmetic Ops

Note:

S0 can be use to indicate Addition or Subtraction.

S1 can be use to indicate the B data input

We have

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