Chapter 4

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# Chapter 4 - PowerPoint PPT Presentation

Chapter 4. Modular Combinational Logic. Decoders. Decoders. n to 2 n decoder n inputs 2 n outputs For each input, one and only one output will be active. Uses: “Minterm generator” Wordline (memory) circuit Code conversion Routing data. 2 to 4 Decoder Example.

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## Chapter 4

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### Chapter 4

Modular Combinational Logic

### Decoders

Decoders
• n to 2n decoder
• n inputs
• 2n outputs
• For each input, one and only one output will be active.
• Uses:
• “Minterm generator”
• Wordline (memory) circuit
• Code conversion
• Routing data

### Design Example

Example
• Using only a 3x8 decoder and two-input OR gates, design a logic circuit which implements the following Boolean equation
Solution

m2

m4

m5

### 2 to 4 Decoder with Enable

2x4 Decoder with Enable
• Enable is abbreviated as EN
• EN is called a Control Signal
• Control Signals can be
• Active High Signal
• EN = 1 – Turns “ON” Decoder
• Active Low Signal
• EN=0 – Turns “ON” Decoder
2 x 4 Decoder with Active High Enable – Truth Table (Short hand notation)

d = don’t care

En has “highest” priority.

If En=0, we “don’t care” about x1 or x0 because Y=0

d = don’t care

En has “highest” priority.

If En=1, we “don’t care” about x1 or x0 because Y=0

### Design Example

Example
• Design a 3x8 decoder using only 2x4 decoders and NOT gates.
Solution

“On” when A=0

“On” when A=1

### Encoders

Encoders
• Opposite of a decoder
• 2n to n encoder
• 2n inputs
• n outputs
• For each input, the circuit will produce an “encoded” output
Example: 4to 2 Binary EncoderTruth Table

Assume only one input high at a time!!

Problems with initial design
• Q: How do we tell the difference between an input of all 0’s (i.e. X=0) and X=1?
• A: Add another output (IA) that indicates that the input is valid. Let’s make IA active low.
Problems with initial design

If IA = 1 => all lines are 0

If IA = 0 => at least one line is 1

• Q: What happens if more than one input is high at the same time?
• A: Design a “priority” encoder that will encode the input with the highest priority.
• Let’s set X3 with the highest priority, followed by X2, X1, and X0
Solution

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Y1

Y0

### Multiplexer/Data Selectors

MUX

Very Important Module!!!

Multiplexer(MUX)/Data Selector
• N to 1 multiplexer
• n data input lines
• Log2(n) control inputs
• One output
• This circuit will “connect” the selected input to the output. The selected input is specified by a decoding of the control inputs.
Example: 4to 1 MUX Truth Table

Control

Inputs

Output

Data Inputs

d = don’t care / Di = data on input i

4 to 1 MUX Equation

D’s are the DATA inputs, AB are control inputs and called

the “select” lines.

4 to 1 MUX Circuit

Control Inputs

Data Inputs

Output

2x4 Decoder

Only a single AND gate will

be “ON” at a time.

4 to 1 MUX Symbol

Data

Inputs

Output

Control

Inputs

Data and Control Paths

Control Path

Outputs

Logic

Data Path

Inputs

Data Path

Outputs

Control Path

Inputs

### MUX Applications

Example
• Using a 4x1 MUX, design a logic circuit which implements:

We have,

Y

Example
• Using a 4x1 MUX, design a logic circuit which implements:

### Multibit Multiplexers

Multi-bit Multiplexers
• J-bit nx1 mux

d0

d1

J bits

deep

d2

J bits

deep

F

dn-1

sel

log2n

j=0 to 3

This is just J separate nx1 multiplexers

Example 4-bit 4x1 MUX

D0[3..0]

D0[3..0]

D1[3..0]

D1[3..0]

F[3..0]

D2[3..0]

F[3..0]

4 bits deep

D2[3..0]

D3[3..0]

D3[3..0]

A B

A

B

j=0 to 3

This is just 4 separate 4x1 muxes

Example
• 4-bit 4x1 MUX

Bit 0

Bit 1

Bit 2

Bit 3

Example 4 bit 4x1 MUX
• For the jth output, we have

D0[j]

D1[j]

F[j]

D2[j]

D3[j]

A

B

Example 4 bit 4x1 MUX
• For the bit 0 output, we have

D0[0]

D1[0]

F[0]

D2[0]

D3[0]

A

B

Example 4 bit 4x1 MUX
• For the bit 1 output, we have

D0[1]

D1[1]

F[1]

D2[1]

D3[1]

A

B

Example 4 bit 4x1 MUX
• For the bit 2 output, we have

D0[2]

D1[2]

F[2]

D2[2]

D3[2]

A

B

Example 4 bit 4x1 MUX
• For the bit 3 output, we have

D0[3]

D1[3]

F[3]

D2[3]

D3[3]

A

B

Example 4 bit 4x1 Mux

Complete Circuit

Bit 0

F[0]

Bit 1

F[1]

F[2]

Bit 2

F[3]

Bit 3

Design Example
• Using a 4bit 4x1 MUX, design a 8bit

4x1 MUX

### DeMultiplexers/Data Distributors

Demultiplexer/Data Distributor
• Opposite of a multiplexer
• 1 to N demultiplexer
• 1 data input
• N data outputs
• Log2(n) control inputs
• This circuit will “connect” a data input to one and only one output. The selected output is specified by a decoding of the control inputs.
Example: 1to 4 DeMUX Truth Table

d = don’t care / Di = data on input i

1 to 4 DeMUX Equations

D is the DATA inputs, AB are control inputs and called

the “select” lines.

1 to 4 DEMUX Circuit

Only one

F will be

active

2x4 Decoder

Only 1 AND gate will

be “ON”

1 to 4 DEMUX Symbol

Selected

Lines

Outputs

Data

Input

Example
• Design a 3x8 decoder using only 2x4 decoders and NOT gates.
Solution

“On” when A=0

“On” when A=1

### Basic Arithmetic Elements

• S=A+B (arithmetic sum)
• S=A+B+C (arithmetic sum)

You can show!!!

Synthesis

Logic Equation

Logic Circuit

Synthesis

Logic Equation

Logic Circuit

A

B

S(0)

C

S(1)

S(0)

S(1)

Simulation

Verification

We verify the circuit via a simulation

Logic Simulation

Inputs

S(0)

S(1)

S 00 01 01 10 01 01 01 11

Outputs

Verification Summary

A

B

S(0)

C

S(1)

Circuit

S(0)

S(1)

Simulation

A

S(1)

B

S(0)

C

Documentation

A

B

S(0)

C

S(1)

Block Diagram

Conceptualization

1

1

1

1111

1111

11110

For the “worst case” we need to add

three bits to generate a single output bit

with a possible carry out.

Can we use our single bit adder for this?

• The circuit gets its name because the carry bit “ripples” from one bit position to the next

A

A

S(1)

S(1)

B

B

S(0)

S(0)

C

C

Conceptualization

First, let’s look at two bits

A(1)

B(1)

Sum(1)

A(0)

B(0)

Sum(0)

A

A

S(1)

S(1)

B

B

S(0)

S(0)

C

C

Conceptualization

Let’s connect the two full adders

A(1)

B(1)

S(1)

Cin

Cout

A(0)

B(0)

S(0)

0

Set carry in for first bit to 0. Why?

0

0

00

00

0

0

000

0

A

A

S(1)

S(1)

0

0

B

B

S(0)

S(0)

C

C

Analysis

Let’s test this for a few cases:

0

0

0

Correct!!!

Rule of thumb: Always test simple cases first!!

1

1

11

11

1

1

110

1

A

A

S(1)

S(1)

0

0

B

B

S(0)

S(0)

C

C

Analysis

Let’s test this for the a few cases

1

1

1

Correct!!!

01

01

010

A

A

S(1)

S(1)

B

B

S(0)

S(0)

C

C

Analysis

Let’s test this for the a few cases

0

0

0

1

1

1

1

1

0

0

Correct!!!

### Subtraction Circuit

Subtraction Circuit
• Calculate 2’s complement of B

Add is a control input. It is active low. This means that the module will compute A+B when Add=0. It will compute A-B when Add=1.

Design using Modules

0

0

1

1

17-18

### Overflow/Underflow Detection

Numerical Overflow/Underflow
• 2’s complement number
• We have S=A+B
• Range of sum
• Overflow occurs if
• Underflow occurs if
Example: Overflow
• Let n=4, Range is
• Let A=\$7, B=\$7, then S=\$7+\$7=\$E, but \$E=%1110 = -2, so Overflow has occurred.
Example: Overflow
• Let’s examine this more closely

-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7

+7

8,9,A,B,C,D,E,F,0,1,2,3,4,5,6,7

So, overflow is the same as “wrap around.”

Example: Underflow
• Let n=4, let A=-7 and B=-7,
• in 2’s complement, A=B=\$9, S=\$9+\$9=\$12=\$02
• so underflow has occurred.
Example: Underflow
• Let’s examine this more closely

-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7

+1

+6

So, underflow is the same as “wrap around.”

Overflow/Underflow Detection
• How do we detect overflow and underflow?
• First adding a positive to a negative number is always OK.
• 4 bit example: 7 + (-8) = -1
• Let’s examine the sum of the MSB’s to determine overflow and underflow.
• Set V=1, if overflow/underflow occurs
Examination of MSB

a,b are the MSBs of A and B. cin is carry in; cout=carry out

Overflow/Underflow Detection
• You can also use
• That is, if for the MSB carry_in is not equal to carry_out, overflow or underflow has occurred.

19-20

### Comparators

Equal Comparator
• Design a logic circuit which will compute

F0 = (A = B)

Solution

You can show,

Not Equal Comparator
• Design a logic circuit which will compute

F = (A <> B)

F = (A = B)

i.e. Just invert our Equal Comparator circuit

Magnitude Comparator
• Design a logic circuit which will compute

F2 = (A>B)

F1 = (A<B)

Let’s develop a truth table for 2-bits

21

### Arithmetic Logic Units (ALUs)

Arithmetic Logic Unit (ALU)

A,B are data inputs of n bits each in depth

S is a control input. We have 2m operations

F is the output

Example
• Let n=4,m=3
• We have A[3..0] and B[3..0]
• With m=3, we have 23 = 8 operations
• Let’s look at a possible function table
Design using a Truth Table
• How large is the truth table?
• 2n from data inputs A and B
• Example: n=8, we have 16 data inputs
• A[7..0] and B[7..0]
• 3 control inputs
• Total of 2n+3 inputs
• N=8, we have 19 inputs
• Our truth table will have
• 192 (361) rows and 8 outputs
• Too complex. Let’s explore another alternative using a “system” or modular approach
Design using Modules
• Note:
• For S2=0, we have logic operations
• For S2=1, we have arithmetic operations
• So, let’s use S2 to control a 2x1 MUX
• to select between logic and arithmetic operations, so our top level design would look like:
ALU Design S2=0

With S2=0, F is the output from

the logic module

ALU Design S2=1

With S2=1, F is the output from

the arithmetic module

### Logic Module Design

Function Table for Logic Module
• S2=0

We can use a 4x1 mux to

implement this module

Logic Module Design

F=AB

AND Operation

S[1..0]=00

0 0

Logic Module Design

F=A+B

OR Operation

S[1..0]=01

0 1

Logic Module Design

F=A

NOT Operation

S[1..0]=10

1 0

Logic Module Design

F=A XOR B

XOR Operation

S[1..0]=11

1 1

### Arithmetic Module

Function Table for Arithmetic Ops

Note:

S0 can be use to indicate Addition or Subtraction.

S1 can be use to indicate the B data input

A

S

B

Arithmetic Module Design

F=A+B

S[1..0]=00

0

0

A

S

B

Arithmetic Module Design

F=A-B

S[1..0]=01

1

0

A

S

B

Arithmetic Module Design

F=A+1

S[1..0]=10

0

1

A

S

B

Arithmetic Module Design

F=A-1

S[1..0]=11

1

1

### Overall Design

We have

Total Design

Logic Module

Arithmetic Module