HCAL Back End Report Manoj Sharan, For BackEnd Group
OUTLINE • Back-End Electronics • Major milestones • Hardware status • Changes in uHTR design and status • Slow controls • Summary & Plans Manoj Sharan 2 2 2 2 2 2 2
HCAL Back-End Groups • Minnesota • Boston • Saha Institue (India) • Delhi Universtiy, Panjab University, Visva-Bharati University • Brown • Maryland • DESY • Albama • RDMS • MSU 3
Back-End Electronics for HF • Replacement of VME based system with uTCA for HF scheduled this year – also support lumi measurement • Our system should be compatible with the present as well as the new front-end electronics system.
Major Milestones • Had a PRR (Feb.) & ESR (June) reviews in 2013. • Review in January 2014 – mini review • Working on feedback from HCAL readiness review in May • Weekly meetings with HCAL management.
Status of Commercial Items • MCH card- 13 +2 • Power module – 24 + 3 • Crate – Vadatech VT892 – 7 of 11 ordered shipped • For HF items delivered and tested. • AMC load card from Samway for testing and burning of Vadatech crates., some spares. • Potential bulk power supply – Power one (Aspiro) • 3 Units delivered and tested • Patch panel plan discussed (modification from TDR) – demands more ac/dc convertors.
uHTR Status • Data links in pre-production cards – • Receivers work at 4.8 Gbps. • Trasnsmitters work at 6.4 Gbps • Tests with CPT7 and oRM successful. • Green light for production received in May. • Enough cards @904 to start full crate operations next week
Modifications in uHTR • 2 + 8 uHTR cards (v 1.3) assembled. • RX0 PPOD performance was poor @6.4 Gbps • But 4.8 gbps performance excellent – met requirements • https://indico.cern.ch/event/319692/ - Frahm/Jeremy • PCB with new design (v 1.4) - under production • Value of 4 resistors changed on power mezzanines • Insufficient trace width in power supply to fpga’s addressed.
Status HF • Booster wires added on v1.3 uHTR’s @MN to address the problem- 6 are now at CERN • Power mezannines for HF 44 sets produced in India, and testing going on – 16 sets already tested. • FPGA – 52 sets in hand and all components purchased • 3uHTR (v. 1.4) pcb’s is completed. Assembly going on Bangalore factory – July first week. • Production of 50 pcb’s v 1.4 underway. • Targeting early August for 50 cards.
uHTR for HB/HE • Power mezannines for HB/HE produced in US • Pre-production of Control Mezzanines for HB/HE + HF completed in US. (10+60) -5 sets have been shipped to India for integration -Rest 50 to be shipped next month to India • Preproduction uHTR in the US is underway
Firmware • New version (a year old from Wisconsin) of MMC (v2.15) have been incorporated into the standard uHTR firmware. It will • -Fix the "many uHTRs" crashing issue • -Allow reloading the firmware from the flash via MMC • -Provide access to the backup FLASH image space. Care to avoid potential corruption of the backup flash image is needed • -Make crate-labelling valid after just an FPGA reload, without -requiring the module to be unplugged and replugged.
Software work and Mapping • Software work on unpacker and electronics map (readiness for 2 anode readout from YETS 2015/2016)- Student from Iowa • We need to understand the question of LUT’s for HF in online database with high priority
AMC13XG(XG=10 Gigabit) • 30 AMC13XG produced and tested – 14 shipped so far • Testing going on a 904 – plans for sending the data to central DAQ via opical link
uTCA rack layout • For HF uTCA crates we will NOT move the existing VME crates but instead utilize the top rack meant for HBHE. • This will avoid fibering work and keep the existing HF VME infrastructure. • The layout – the panel ( Aspiro power supply) for -48 V supply to uTCA crates will be done by technicians soon. • The uTCA crate no. = VME + 20
Optical Margin Tests @904 & P5 • Optical Sensitivity Verification of PPOD • Results for batch of 24 PPOD’s analysed. • They are not as good as the first batch (BB • series), but not as bad as the next (BC).
Slow Controls • A preliminary version of uTCA slow controls is ready (next slide) – MSU & DESY - WinCC OA (formerly PVSS) sytem at 904 using the HCAL uTCA crates there. Used a windows PC which is not publicly accessible. • ngFEC work (DESY)- whole chain is working • GLIB card – end of production • Replacement card – FC7 is proposed – to be made available in next few months
Condition database Configuration database PVSS (WinCC OA) control, monitoring, visualization Connection to microTCA electronics is realized as a chain PVSS – DIM server – System Manager - mTCA PVSS DIM client DIM server DIM server and WinCC OA project are developed and installed on WIN7 (64 bit) machine Wisconsin System manager works under LINUX Software are debugged and checked on DESY test-stand and HCAL test-stand in Bld. 904 Wisconsin system manager 10/19/2019 G. Bogdanova V. Volkov MSU 18
ngFEC work • Whole chain: ngCCMserver <-> ngFEC uTCA crate <-> GLIB <-> ngCCM <-> QIE10 bridge fpga is working • Command line tool to set/get all registers by name available • interface for epics graphical user interface Configuration ngCCMserver IPbus I2C AMC13 GLIB ngCCM QIE10 Bridge ngFEC
Plans for Slow Controls • Plans to install slow control project @904 and connect it to test stand. • Windows 7 (64 bit machine required ) • In autumn continue @ Point 5 – 2 computers would be required • ngFEC work • Replacement card FC7 - experience • A dedicated uTCA crate @ 905/P5 for development & integration.
Summary • Significant progress this year. • Will start full crate operations next week. • We expect to have stable operations by August
HF VME Crates CMS HCAL s2f02/top HF S2-13 Phi=10-130 CMS HCAL s2f05/bottom HF S14-25 Phi=130-250 CMS HCAL s2f07/top HF S26-36, 1 Phi=250-10
AMC 13 • A new firmware to support 1,2 or 3 independent event builders each feeding a separate DAQ link • Will remove the limit on event fragment size from each AMC card • Will include the final CDAQ link firmware, supporting 3 links (will then get a good idea of resource useage) • First attempt at full crate test in 904 – problem in clock/TTC alignment – (firmware soln. already there) • A new release of the T2 board is planned – and funding has been released for the prototype new design • Based on aggreement on Funding for AMC13 project – production of new batch of modules.
Power-Mezzanine Testing @Saha PM is mounted on the test board built by Minnesota The configuration allows us to monitor the temperature, voltage and current drawn by the PM/APM Test carried out for 39 hrs for each PM/APM to monitor its stability 2 more boards, have been setup which will be used for production and pre-testing.