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Gamma-ray Large Area Space Telescope. GLAST Large Area Telescope: Electronics, Data Acquisition & Instrument Flight Software Peer Critical Design Review March 19-20, 2003 Gunther Haller Stanford Linear Accelerator Center Manager, Electronics, DAQ & FSW LAT Chief Electronics Engineer

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Gamma-ray Large Area Space Telescope

GLAST Large Area Telescope:

Electronics, Data Acquisition & Instrument Flight Software

Peer Critical Design Review

March 19-20, 2003

Gunther Haller

Stanford Linear Accelerator Center

Manager, Electronics, DAQ & FSW

LAT Chief Electronics Engineer

[email protected]

(650) 926-4257

Cdr agenda
CDR Agenda

Day 1 - March 19 (all times PST)

Section 1: Electronics, DAQ, FSW Overview 8:00 – 8:40

Section 2: Management 8:40 – 9:20

Section 3: System Engineering 9:20 – 10:30

BREAK 10:30 – 10:45

Section 4: Electronics 10:45 – 12:00

LUNCH 12:00 – 13:00

Section 5: Instrument Software Overview 13:00 – 13:30

Section 6: Instrument Software I 13:30 – 14:45

BREAK 14:45 – 15:00

Section 7: Instrument Software II 15:00 – 15:30

Section 8: Instrument Software III 15:30 – 16:15

Discussion 16:15 – 17:00

Cdr agenda con t
CDR Agenda (Con’t)

Day 2 - March 20

Section 9: Mechanical & Thermal 8:00 – 9:00

Section 10: Power - EMI 9:00 – 9:30

Section 11: Monitoring & Thermal Control 9:30 – 10:00

BREAK 10:00 – 10:10

Section 12: EEE Parts 10:10 – 10:40

Section 13: Manufacturing 10:40 – 11:10

Section 14: Summary 11:10 – 11:20

Discussion/Closeout 11:20 – 12:00

Adjourn 12:00

Review board team
Review Board Team

  • Hartmut Sadrozinski/UCSC Chairman

  • Al Vernacchio/GSFC Co-Chairman - GLAST Deputy Project Manager

  • Fred Huegel /GSFC Electrical Engineering

  • John Fox/SLAC Electrical Engineering - Applied Physics

  • Steve Smith/SLAC Electrical Engineering – System Engineering

  • Bob Jackobsen/LBL Software

  • Rick Schnurr/GSFC Software

  • Lowell Klaisner/SLAC LAT Chief Engineer

  • Steve Scott/GSFC Systems Engineering

  • Ron Zellar/GSFC Software

Gamma-ray Large Area Space Telescope

GLAST Large Area Telescope:

Electronics, Data Acquisition & Flight Software


Gunther Haller

Stanford Linear Accelerator Center

Manager, Electronics, DAQ & FSW

LAT Chief Electronics Engineer

[email protected]

(650) 926-4257

Overview outline
Overview Outline

  • Overview of LAT and Electronics

  • Level III Requirements Summary

  • Meeting Key Requirements

  • Flowdown – Requirements to Design

  • Design Evolution

  • Optimization

  • Technical Heritage

  • Status of July DPDR Recommendation Items

Overview of lat



Overview of LAT

  • Precision Si-strip Tracker (TKR) 18 XY tracking planes. Single-sided silicon strip detectors (228 mm pitch) Measure the photon direction; gamma ID, ~880,000 channels.

  • Hodoscopic CsI Calorimeter(CAL) Array of 1536 CsI(Tl) crystals in 8 layers. Measure the photon energy; image the shower.

  • Segmented Anticoincidence Detector (ACD) 89 plastic scintillator tiles. Reject background of charged cosmic rays; segmentation removes self-veto effects at high energy.

  • Electronics System Includes flexible, robust hardware trigger and software filters.


ACD [surrounds 4x4 array of TKR towers]


DAQ Electronics

Systems work together to identify and measure the flux of cosmic gamma rays with energy 20 MeV - >300 GeV.

Lat electronics
LAT Electronics

TKR Front-End Electronics (MCM)

16 Tower Electronics Modules

  • DAQ electronics module (DAQ-EM)

  • Power-supplies for tower electronics

ACD Front-End Electronics (FREE)

CAL Front-End Electronics (AFEE)



Global-Trigger/ACD-EM/Signal-Distribution Unit*

3 Event-Processor Units (2+1 spare)

  • Event processing CPU

  • LAT Communication Board

  • SIB

Spacecraft Interface Unit

  • Spacecraft Interface Board (SIB): Spacecraft interface, control & data

  • LAT control CPU

  • LAT Communication Board (LCB): LAT command and data interface

Power-Distribution Unit (PDU)*

  • Spacecraft interface, power

  • LAT power distribution

  • LAT health monitoring

* Primary & Secondary Units shown in one chassis

Level iii key requirements summary
Level III Key Requirements Summary


Ref: LAT-SS-00019

Level iii key requirements summary 2
Level III Key Requirements Summary (2)

Power System

Ref: LAT-SS-00136

Evolution of daq design
Evolution of DAQ Design

Proposal Design:

  • No global trigger, ability to reduce hardware trigger rate from tracker marginal

  • Data router to move partial event fragments into central processor

  • Event building in software

  • 16 processors, one on each tower to process data

  • Communication to TKR/CAL/ACD systems very unique

Current Design:

  • Global trigger, ability to reduce hardware trigger rate from tracker

  • Event building in hardware

  • Data switch to move complete event fragments from hardware event builder to processor

  • 2 processors for event processing

  • Communication to TKR/CAL/ACD systems unified

Optimization summary
Optimization – Summary

  • Serial LVDS (Low-Voltage-Differential-Swing) protocol with Data, Clock, Reset, Return-Data to each front-end system and between DAQ modules (see LAT-TD-00606)

  • Buffering of event data fragments at each module stage to meet dead-time requirements

    • TKR front-end -> TEM -> Event-Builder -> LAT Communication Board -> CPU -> Spacecraft Solid-State Recorder

  • Flow-control between buffer stages to meet non-overwriting and data consistency requirements

  • Utilization of ASIC’s to meet volume, power, and cost constraints


  • Similar data-acquisition system was used on balloon flight (TEM, one event-processing CPU, one spacecraft-interface-equivalent control CPU)

  • Electronics components: mostly components with flight-heritage (FPGA’s, LVDS converters, memories)

  • ASIC technology same as for tracker, calorimeter, ACD systems

  • Trigger, dataflow, event assembly, and event filter processing very similar to past high-energy physics experiments

Summary of july delta pdr review
Summary of July Delta-PDR Review

  • “The electronics including software was already baselined at the January PDR review”

  • “Work with GSFC branch to qualify poly-switches for use in the LAT electronics”

    • Approved

  • “Ensure that FPGA design practices adhere to GSFC guidelines and recommendations for space-flight applications”

    • Working with Rich Katz at GSFC to review LAT FPGA designs. In process of sending designs to GSFC for review

Summary of july delta pdr review con t
Summary of July Delta-PDR Review (Con’t)

  • “Determine the need date for processor down-select based on software design impact”

    • Have selected BAE RAD750

  • “Finalize the flight-software management plan and test plan”

    • Flight software management plan (LAT-MD-00104-02) entered into cyberdocs 6 November 2002

    • Flight software test plan (LAT-TD-00786-01) entered into cyberdocs 10 June 2002

Summary of july delta pdr review con t1
Summary of July Delta-PDR Review (Con’t)

  • “Identify solution path to replace the functionality that would have been provided by SCL COTS tool in the flight software. Coordinate with I&T and mission operations”

    • I&T has adopted a low level toolset (Python, Qt, XML, MySQL) to implement the EGSE side of the I&T test environment. FSW provides the hardware drivers for the embedded system. Code already exists and is running on test stands to replace the SCL register manipulation model. FSW has adopted the I&T low level toolkit for its Test Executive.

Gamma-ray Large Area Space Telescope

GLAST Large Area Telescope:

Electronics, Data Acquisition & Flight Software


Gunther Haller

Stanford Linear Accelerator Center

Manager, Electronics, DAQ & FSW

LAT Chief Electronics Engineer

[email protected]

(650) 926-4257

Management outline
Management Outline

  • Team Leads

  • Team Partners

  • Contingency (Mass, Power, Cost)

  • Organization Chart

  • Work Flow

  • Testing Overview

  • Fabrication Plan

  • Schedule & Critical Path

  • Cost

  • Procurements

  • Configuration Management

  • Issues and Concerns

  • Summary

Team leads
Team Leads

  • Gunther Haller

    • Project Manager Electronics, DAQ, Instrument Software

    • Chief Electronics Engineer

    • PCMS Schedule & Cost Lead

  • JJ Russell

    • Instrument (Flight) Software Lead

  • Mike Huffer

    • Data-Acquisition System Lead

  • Dave Nelson

    • Mechanical & Thermal Engineering Lead

    • I&T Lead

    • Power/EMI System Lead

  • Jobe Noriel

    • Packaging Engineering Lead

  • Jerry Clinton

    • Manufacturing Lead

  • Nick Virmani/Darren Marsh

    • Mission/Quality Assurance

Team partners
Team Partners

  • Naval Research Lab

    • Spacecraft interface board (Silver Engineering)

    • Instrument flight software (Boot Code, SC Interface)

    • CAL front-end electronics

  • University of Santa-Cruz

    • Tracker front-end electronics

  • Goddard Space Flight Center

    • ACD front-end electronics

Contingency handling
Contingency Handling

  • All contingency (Power, Mass, Cost) is held at LAT project level

  • Change requests to LAT Change Control Board are required to account for variance

  • 4.1.7 Changes which required increase in cost, mass, power:

Organization charts
Organization Charts

Electronics, DAQ & Flight Software

G. Haller


WBS 4.1.7


Quality Assurance



D. Nelson

D. Marsh/N. Virmani

M. Huffer

M .Freytag









Instrument Software

Power System

GSE & Operation

Instrument I&T

D. Nelson

J. Russell

M. Huffer

G. Haller







WBS 4.1.7.A

WBS 4.1.7.C

Front-End Elex

G. Haller


Tracker Elex

WBS 4.1.4

CAL Elex

WBS 4.1.5

ACD Elex

WBS 4.1.6

Section 7.4 Elec, DAQ, Flt SW Overview

Development testing lat system
Development Testing LAT System

COM-card 1: LAT Communication Module

COM-card 2: Trigger Module

  • Processor: Motorola Power-PC

  • Flight Software

  • LAT COM engineering modules for

    • LAT Communcation

    • Trigger

  • TEM DAQ Assembly

  • TEM Power-Supply Assembly

  • 28-V Supply

  • LAT-TD-00861

Power-PC Processor

Flight Software

TEM DAQ Assembly

Tower Power Supply Assembly

(1.5V/2.5V/3.3V/ 0-100V/0-150V)

28-V Power Supply

Testing plan
Testing Plan

  • ASIC’s are 100% acceptance tested before assembly on boards

    • Radiation performance is lot tested for single event effects and total ionizing radiation.

  • Function/Performance is tested at the board level

  • Qualification and acceptance tests including performance, vibration, EMI/EMC, and thermal vacuum are performed at the component sub-assembly (box) level.

Fabrication plan
Fabrication Plan

  • ASIC’s

    • Design: SLAC

    • Fabrication: Agilent

    • Packaging: ASAT

  • Printer-Circuit Boards

    • Design:

      • Spacecraft Interface Board: Silver Engineering

      • All other DAQ custom modules: SLAC

    • Fabrication: qualified vendor

    • Parts procurements: SLAC

    • Assembly: qualified vendor

  • Enclosures

    • Design: SLAC

    • Fabrication: qualified vendor

  • Module Assembly (PCB’s/cables/enclosure)

    • Design: SLAC

    • Assembly: qualified vendor

  • Tower Power Supplies

    • Circuit & board design, fabrication, assembly: qualified vendor

    • Enclosure design: SLAC

    • Assembly: qualified vendor

  • Harness

    • Design: SLAC

    • Assembly: qualified vendor

  • Installation at SLAC

Work flow
Work Flow


First layer DAQ modules


TEM DAQ Assembly

Acceptance Test

TEM DAQ Enclosure

TEM Assembly

LAT Integration 1st stage

TEM PS Board

TEM PS Assembly

Acceptance Test

TEM Power Supply Enclosure



GASU Assembly

Acceptance Test

Second layer DAQ modules

GASU Enclosure

LAT Integration 2nd stage



PDU Assembly

Acceptance Test

PDU Enclosure

SIB Board

SIU Assembly

Acceptance Test

Add Harness


LCB Board

LAT Integration 3rd stage

Acceptance Test

CPU Board

EPU Assembly

PS Board

Acceptance Test

Crate Enclosure


Acceptance Test


Critical path
Critical Path

  • TEM DAQ Assembly

    • Flight TEM DAQ PC Board fab and loading Feb 04

      • Requires flight TEM ASICs

  • Tower Power Supplies

    • Flight assemblies by March 04

      • Is out for RFP, expected back March 25

        • Depends on vendor response

Cost by fiscal year
Cost by Fiscal Year

  • W.B.S. 4.1.7 without contingency

Cost contingency and schedule
Cost Contingency and Schedule

  • Status below is as of Jan 31-03

  • Software-specific contingency: see Instrument Software presentation

*contingency is held at project level

Manpower plan
Manpower Plan

4.1.7 Electronics



  • Long-Lead Procurements

    • Tower power supplies (RFP close March 25)

    • Processor (RFP in April)

    • Voltage regulators (after CDR)

  • Major Upcoming Procurements Near-Term (< 4 months)

    • FPGA’s

    • Connectors

    • MOS Transistors

    • DC/DC Converters & Filters

    • ASIC’s

  • Major Upcoming Procurements Long-Term (>4 months)

    • Enclosures

    • Harness

  • Minor Upcoming Procurements

    • Miscellaneous electrical components

Configuration management and information technology
Configuration Management and Information Technology

  • SLAC CM System

    • Cyberdocs (web-based document storage): Electronically stored documents, drawings, procedures, Work-Order-Authorization (WOA’s)

    • Risk Item Database

    • Document Library

  • Electronics, DAQ, Flight Software web-site


    • Website is used to share information and store draft documents,

    • Directly access CM documents stored in cyberdocs

Issues and concerns
Issues and Concerns

  • Schedule is very tight

    • Critical path has little room for delay

  • Dependency on delivery of procured items


  • Technically the electronics and instrument software are on track

  • Schedule and budget plan are fully in PCMS down to level 7 since PDR, both are on track

  • Critical path and contingency analyzed

  • No unusual risks besides risks of any high-energy physics experiment and space flight instrument

  • Testing, fabriation, and workflow plans in place

  • Experienced management and technical team