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##### Multilevel Logic Synthesis -- Introduction

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**Multilevel Logic Synthesis: Outline**• Introduction • What is multilevel logic? • Why we need it? • Problems and challenges. • Multilevel Logic Synthesis and Minimization • Restructuring • Technology Independent Local Optimization • Technology Mapping • Delay Analysis and Optimization (*) ENEE 644**c**d a’ G F d’ F’ e f b Multilevel Logic vs. Two-Level Logic Example: Let F=a’b+ab’, define G and H as follows: if F is true, then G=cd+a’d’, H=cd+a’d’+e(f+b), else G=e(f+b), H=(cd+a’d’)e(f+b). Multi-Level Implementation: G=F(cd+a’d’)+F’e(f+b) 4-level H=F(cd+a’d’+e(f+b))+F’(cd+a’d’)e(f+b) 5-level ENEE 644**Multilevel Logic vs. Two-Level Logic**Example: Let F=a’b+ab’, define G and H as follows: if F is true, then G=cd+a’d’, H=cd+a’d’+e(f+b), else G=e(f+b), H=(cd+a’d’)e(f+b). G = F(cd+a’d’)+F’e(f+b) = (a’b + ab’)(cd + a’d’) + (a’b + ab’)’(e)(f + b) = a’bcd + a’bd’ + acdb’ + e(f+b)(a+b’)(a’ +b) = a’bcd + a’bd’ + acdb’ + (efa + efb’ + eba)(a’+b) = a’bcd + a’bd’ + acdb’ + efab + efb’a’ + eba THIS IS MORE COMPLICATED TO IMPLEMENT ENEE 644**Multilevel Logic vs. Two-Level Logic**Two-level: • At most two gates between a primary input and a primary output. • Real life circuits: PLA. • Exact optimization methods: well-developed, feasible. • Heuristics. Multi-level: • Any number of gates between a primary input and a primary output. • Most circuits in real life are multilevel (e.g. standard cells, FPGA). • Smaller, less power, and (in many cases) faster. • Exact optimization methods: few, high complexity, impractical. • Heuristics. ENEE 644**Optimization Objectives**• Area: occupied by the logic gates and interconnect, e.g. measured by “one literal = one transistor” in technology independent optimization. • Delay: measured by the longest path (critical path) through the logic. • Power Consumption Optimization is performed while simultaneously satisfying upper/lower bound constraints placed on these physical quantities. ENEE 644**Optimization Cost Criteria**(Figure source: Prof. Brayton’s lecture notes.) ENEE 644**Technology Independent**• A design is technology independent when the formula (function, system) has no connection with the building blocks in the implementation. • Advantage: cost can be simply estimated by the number of logic symbols (I.e. one literal = one transistor), delay is the length of the “critical path”, better for local optimization. • Example: Full Adder • z(x,y,c) = XOR(x,y,c) = xyc+x’y’c+x’yc’+xy’c’ • cnew(x,y,c) = Majority(x,y,c) = xy+(x+y)c • The literal count is 12+5=17 • The critical path delay is 3: xx+y(x+y)ccnew • A design is technology independent when the formula (function, system) has no connection with the building blocks in the implementation. • Advantage: cost can be simply estimated by the number of logic symbols (I.e. one literal = one transistor), delay is the length of the “critical path”, better for local optimization. • A design is technology independent when the formula (function, system) has no connection with the building blocks in the implementation. ENEE 644**signal**formula gate transistors g (xy)’ NAND 4 a g’ NOT 2 b (x+y)’ NOR 4 e (a+b)’ NOR 4 z e’c+ec’ XOR 8 d b’ NOT 2 h (dc)’ NAND 4 f h’ NOT 2 j (a+f)’ NOR 4 cnew j’ NOT 2 Technology Dependent • A design is technology dependent if the formula (function, circuit, system) is implemented by one or more logic gates in a pre-designed set of gates (called technology library or cell library). • Advantage: gates in the cell library have a highly optimized, pre-defined path to silicon, so that the area and delay parameters are known and accurate. • Example: Full Adder ENEE 644**Multilevel Logic Synthesis Problem**• Goal: • Model the multilevel logic • Optimize the logic based on the cost criteria • Difficulty: • Multilevel gives more design freedom and increases the design complexity • Technology dependent/independent views • Models: • Algebraic forms • Boolean networks • Optimization Techniques: HARD • Exact method: few, exponential complexity, impractical • Approximation method: heuristic algorithm, rules-based methods ENEE 644**Sum of Products (SOP)**• Example:abc’+a’bd+b’d’+b’e’f • Advantages: • Easy to manipulate and minimize. • Algorithms available (e.g. AND, OR, TAUTOLOGY). • Two-level theory applies. • Disadvantages: • Not representative of logic complexity. For example f=ad+ae+bd+be+cd+ce f’=a’b’c’+d’e’ which differ in their implementation by an inverter. • Difficult to estimate logic and to estimate progress during logic manipulation. ENEE 644**Factored Forms: Overview**• Example:(ad+b’c)(c+d’(e+ac’))+(d+e)fg • Advantages: • Good representative of logic complexityf=ad+ae+bd+be+cd+ce=(a+b+c)(d+e) f’=a’b’c’+d’e’ • Good estimator of logic implementation complexity • Implicitly Imply Multi-Level Computation (Computation using tree) • Disadvantages: • Not many algorithms available for manipulation • Not canonical: ab+c(a+b)=bc+a(b+c)=ac+b(a+c) ENEE 644**Example:**• Factored forms: x, y’, abc’, ab+c’, ((a’+b)cd+e)(a+b’)+e’. • However, (a’+b’)’c’ is not, although it equals abc’. This is because internal complement in not allowed Factored Forms: Definition A factored form is defined recursively by the rules: • A product is either a single literal or a product of factored form. • A sum is either a single literal or a sum of factored forms. • A factored form is either a product or a sum Another point of view: • p l (1) (base case) • p f*f (2) • s l (3) (base case) • s f+f (4) • f p (5) • f s (6) ENEE 644**Factoring Tree**• Factored forms can be graphically represented as labeled trees, called factoring trees, in which each internal node including the root is labeled with either +or·, and each leaf has a label of either a variable or its complement. • Example: ((a’+b)cd+e)(a+b’)+e’ + e’ · + + e a b’ · c d + a’ b ENEE 644**+**+ · · · · a a b c b c + + b c a b Equivalent Factorizations • Two factored forms are equivalent if they represent the same logic function. • Example: a(b+c)+bc and ab+c(a+b) • Two factored forms are syntactically equivalent if their factoring tree are isomorphic. (WHAT IS ISOMOSRPHIC?) • Example: (a+b)(c+d)e and (c+d)e(a+b) a(b+c)+bc and ab+c(a+b) ENEE 644**+**· · a a c b Maximal Factorizations • A factored form is maximally factored if • For every sum of products, there are no two syntactically equivalent factors in the products; • For every product of sums, there are no two syntactically equivalent factors in the sums. • Example: • ab+ac is not maximally factored, a(b+c) is. • (a+b)(a+c) is not maximally factored, a+bc is. ENEE 644**Optimum Factored Forms**• The size of a factored form f, (f), is the number of literals in the factored form. • Example: • ((a+b)ca’) = 4 • ((a+b+cd)(a’+b’)) = 6 • A factored form is optimum if no other equivalent factored form has fewer literals. • Example: • ab+a’c+bc is not optimum (ab+a’c+bc = ab+a’c). ENEE 644**Unate Factored Forms**• A factored form F is positive unate in x,if x appears in F, but x’ does not. A factored form is negative unate in x,if x’ appears in F, but x does not. F is unate in either case, and is binate if it is not unate. • Example: • (a+b’)c+a’ is (positive) unate in c, (negative) unate in b, and binate in a. ENEE 644**Cofactor of Factored Forms**• The cofactor of a factored form F with respect to a literal x (or x’ ) is the factored form Fx= Fx=1(x) (or Fx’=Fx=0(x) ) obtained by: • replacing all occurrences of x by 1, and x’ by 0 • simplifying the factored form using the Boolean algebra identities 1y=y 1+y=1 0y=0 0+y=y • after constant propagation (all constants are removed), part of the factored form may appear as G + G. In general, G is another factored form, and the G’s may have different factored forms. ENEE 644**Cofactor of Factored Forms**• The cofactor of a factored form F with respect to a cube c is a factored form obtained by successively cofactoring F with each literal in c. • Example: • F = (x+y’+z)(x’u+z’y’(v+u’)) and c = vz’ Fz’ = (x+y’)(x’u+y’(v+u’)) Fz’ v = (x+y’)(x’u+y’) ENEE 644**Algebraic and Boolean Expressions**• f is an algebraic expression if f is a set of cubes (SOP), such that no single cube contains another (minimal with respect to single cube containment). Otherwise, f is called a Boolean expression. • Example: a+bc is algebraic, a+ab is Boolean. (ab+a’c+bc???) • Special Properties of Boolean Algebra: • a+a = a·a = a • a+bc = (a+b)(a+c) • a+ab = a • The support of an expression f, supp(f), is the set of variables that fexplicitly depends on. Two expressions f and g are said to be orthogonal if supp(f)supp(g)=, denoted byfg. • Example: a+b c+d ENEE 644**Algebraic and Boolean Factored Forms**• A factored form f is said to be algebraic if the SOP expression obtained by multiplying f out directly(I.e. without using aa=a+a=a, aa’=0, a+ab=a) is algebraic, otherwise it is Boolean. • Example: abg+acg+adf+aef+afg+bd+ce+be+cd • (b+c)(d+e)+((d+e+g)f+(b+c)g)a =(bd+be+cd+ce)+(df+ef+gf+bg+cg)a = bd+ce+be+cd+abg+acg+adf+aef+afg (algebraic) • (b+c)(d+e+ag)+(d+e+g)af (algebraic) • (af+b+c)(ag+d+e) =afag+afd+afe+bag+bd+be+cag+cd+ce =afg+adf+aef+abg+acg+bd+be+cd+ce (Boolean) ENEE 644**Value of a Factorization**• Given an algebraic factorization F=G1G2+R, its factorization value is given by: fact_val(F,G2) = lits(F)-(lits(G1)+lits(G2)+lits(R)) where lits(F) and cubes(F) are the number of literals and cubes in SOP form of F respectively, G1,G2, and R are algebraic expressions. • Example: The algebraic expressionF = ae+af+ag+bce+bcf+bcg+bde+bdf+bdg can be expressed in the form F = (a+b(c+d))(e+f+g), which requires 7 literals, rather than 24, a save of 17 literals. If G1=(a+bc+bd) and G2=(e+f+g), then R= and fact_val(F,G2) = 23+25=16.Where the extra literal saving comes from? ENEE 644