1 / 31

FPGA firmware  of DC5 FEE

DC5 FPGA firmware review 2014/5/15. FPGA firmware  of DC5 FEE. Chih-Hsun Lin, Yu-Sheng Teng , Ming-Lee Chu, Chia-Yu Hsieh, Takahiro Sawada , Wen-Chen Chang Institute of Physics, Academia Sinica , Taiwan

baba
Download Presentation

FPGA firmware  of DC5 FEE

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. DC5 FPGA firmware review 2014/5/15 FPGA firmware of DC5 FEE Chih-Hsun Lin, Yu-Sheng Teng, Ming-Lee Chu, Chia-Yu Hsieh, Takahiro Sawada, Wen-Chen Chang Institute of Physics, Academia Sinica, Taiwan Tobias Grussenmeyer, Horst FischerInstitute of Physics, University of Freiburg, Germany

  2. Outline • System architecture • Module connection • Signal/CLK connection • FPGA design • FEM • TDC measurement • Trigger match • DCM • Data packing and transfer • List of identified problems during the on-site test • Summary

  3. FEM-DCM Architecture • FPGA in FEM (LFXP2-8E-6FT256C) • 12 EBR Blocks (221184 bits) • FPGA in DCM (Spartan-6 xc6slx45t-3fgg484) • 116 18Kb RAM Blocks = 232 9Kb RAM block

  4. Module Connection Ethernet cable Optical fiber x8 x1 x20 Master CLK GANDALF DCM FEM Optical Tx Command & FLT Optical Rx Data …… FEM Signal and Clock rate — Optical Tx and Rx 3.1104Gbps — Master CLK 38.88 MHz (was 155.52MHz) — Command 38.88 Mbps (was 155.52MHz) — FLT (First level Trigger) Pulse sync to 38.88MHz CLK — Data 155.52 Mbps Totally 1 GANDALF 8 DCM 160 FEM

  5. Experimental Parameters • Highest hit rate per wire = 200 kHz • Noise rate per wire = 10 kHz (conservative estimation based on the measured value at 4 fC threshold) • Overall hit occupancy = 10 % • Trigger matching window = 200 ns • Highest instantaneous trigger rate = 100 kHz, i.e. minimum time between two consecutive triggers = 10 μs. • Trigger latency = 8 μs • We will use these parameters to evaluate the proper specifications of FEE.

  6. Data Transfer • FEM  DCM • Data format : 32 bits • Header : 2 bits • FEM ID (0-19): 6 bits • channel ID (0-15): 4 bits • Time (range 70 s, finest 1-ns resolution): 16 bits • PLL locked: 4 bits • Speed = 155.52 Mbps • Maximum transmission time per trigger = 32bits/word * (16+2) words / 155.52 Mbps ~ 576 bits/ 155.52Mbps ~ 3.7 μs < 10 μs trigger period • Minimum cyclic buffer size :(200+10) kHz *16 hits * 8μs~ 30 hits < 512 hits buffer size • DCMGANDALF • Speed = 3.11 Gbps • Maximum transmission time per trigger = 32bits/word * [(16+2) words *20 FEM + 5 S-link header words]/ 3.11 Gbps ~ 11680 bits/ 3.11 Gbps~ 3.8 μs < 10 μs trigger period • GANDALF ROB • Speed : 160 MByte/s = 1.28 Gbps • Maximum transmission time per trigger = 32bits/word * [(16+2) words *20 FEM + 5 S-link header words]* 8 DCM *10% occupancy/ 1.28 Gbps ~ 9344 bits/ 1.28 Gbps ~ 7.3 μs < 10 μs trigger period

  7. Clock Structure DCM FEM Rx clock 155.52M Deformater PLL1 FEM Ctrl Logic Xilinx Transceiver Clock 38.88M 77.76M GANDALF Optical Tx Align Comma K28.1 k28.5 Optical Rx FEM2DCM transmit 155.52MB 155.52M OSC 155.52M 233.28M PLL2 TDC 233.28M 90° 2M CMAD setting • Deformater is a VHDL code from T. Grussenmeyer. • Master 38.88MHz CLK is generated and phase adjusted by RX CLK and command from GANDALF. • Two TDC CLKs will be 233.28MHz = 38.88MHz x 6. (248MHz now) • 155.52MB is a phase adjustable CLK for data output.

  8. First Level Trigger • In DCM, First level trigger is generated according to a specific command/data pattern from GANDALF. • A FLT pulse is distributed to FEMs sync to master CLK. Rx clock 155.52M Deformater Xilinx Transceiver Clock 38.88M GANDALF Optical Tx FLT Comma K28.0 Optical Rx FLT(first level trigger)

  9. TCS Reset signal • TCS reset will be distributed to FEMs by a dedicated command sync to master CLK. • Implemented on DCM and FEM. • A command to FEMs to reset TDC counters in the current implementation. • Need inputs about TCS Reset command/pattern from GANDALF.

  10. FEM TDC Block Diagram x16 x16 Time CMAD x16 inputs Buffer Ctrl Logic Cycling buffer (512 hits) TDC x16 Flag x16 Reset # of TDC hits Command handler Write point Data Trig Flag x1 Trig Time Trigger Logic Trigger Match Event FIFO (512 x 32bit) DCM & FEM (8b/10b) Link logic Trig Flag Flag TDC FLT trigger Trig Time Reset It will be 4096x32 bit. 0100110110 Serial data

  11. TDC counter • TDC value for each hit is 16 bit. • MSB 14 bit is from a counter by 233MHz CLK. • LSB 2 bit is determined by a four bit pattern latched with 233MHz CLK and 233MHz 90o CLK. 14 bits 2 bits 14 bits ≈ 70.3us 233.28M 233.28M 90° 1 unit = 1.07ns

  12. Trigger Match Twindow wire • Data and control parameters: • TDC time = 16 bit (1ns lsb) [maximum 70 s] • Trigger Latency = 12 bit (4ns lsb) [maximum 16 s] • Matching Window = 12 bit (4ns lsb) [maximum 16 s] • (Ttrig–Tlatency–Twindow) < Thit < (Ttrig–Tlatency+Twindow) • Matching process stops at either one of the following three conditions: • 16 matched hits. • No more TDC hit for matching(Max hits for matching process is 255). • 4 unmatched hits after last matched hit. All the parameters for these three conditions could be adjusted and optimized according to the realistic experimental conditions. FLT Tlatency Thit Ttrig

  13. DCM block diagram x20 x20 x20 x20 x20 FLT(first level trigger) DCM & FEM (8b/10b) Receiver DCM to FEM Command FIFO FEM to DCM Data FIFO (512 x 32bit) 1bit Event Counting FIFO DCM & FEM (8b/10b) Transmitter Command handler GANDALF DCM Link logic command 010011 Serial data data packing TCS info 010011 Serial data data Transceiver 010011 Serial data

  14. Current data-packing procedure in DCM Power on reset Idle Scan FEM FIFO Any FEM frame valid frame valid No No Yes Yes Readout FEM data Wait up to 4 system clocks No EOF word Timeout or all FEM valid No Yes Yes No All FIFOs scaned Send S-link begin mark Yes Send S-link header Send S-link end mark

  15. List of Identified Problemsduring the on-site test • Data loss (DCM to GANDALF) • Command error (DCM to FEM) • Command lost (PC with USB connection to GANDALF)

  16. Data Loss issue(DCM to GANDALF) • Previous version of DCM FPGA design, the same state machine controls both command flow and data flow. • Whenever a command arrives in DCM, the data packing and transmission is interrupted. This is the found cause of the data loss. • Solution: The DCM FPGA design is modified to have independent control for: • Command flow (GANDALF DCM  FEMs) • Data flow (FEMs  DCM  GANDALF)

  17. Latest Data transmission Test(with new DCM firmware) 1. Pass command Trigger_on to DCM 2. DCM generates 100k trigger in one sec. • Test result • DCM did receive 100k data frames from FEM. • There is a loss of 1.5% data frame for the data recorded in PC and the cause is likely the current USB I/O capability. The data rate for 100k Hz trigger test is 100k*4 byte per word* 23 words per FEM = 9.2 MB/sec. x1 x1 x1 GANDALF Optical fibre DCM Ethernet cable FEM USB Count mode 4. Packing data frame and pass to GANDALF 3. FEM send 1 data frame to DCM per trigger 7. Save data into file and use program analysis 6. Pass data frame to PC 5. Use counter check valid data frame number from FEM

  18. Command Error issue(DCM to FEM) • A timing issue, long operational logic pathdue to • 8b/10b encoding • Multiplexing of commands and fill pattern • Solution: Pipeline/FIFO is added in the DCM FPGA design to reduce logic path. • Test done. All 20 FEM ports work correctly.

  19. Command lost issue(PC with USB connection to GANDALF) • DCM could not 100% successfully receive the control command issued from PC via GANDALF if PC is reading data from GANDALF and sending commands to GANDALF simultaneously.This is due to the handshaking of USB port between PC and GANDALF. It is not a valid issue for the reality where the data control is via the VME backplane. • Solution: Make sure that the trigger is properly stopped before sending any other control commands.

  20. Summary • The proper functioning of clock/command/data chain in the current FPGA firmware is verified and the optimization study will continue. • All identified problems of digital transmission during the on-site test have been investigated and solved. • We trust that the current FPGA firmware and the hardware design overall do fulfill the experimental requirements of DC5 FEE. It should be reasonable to move toward the stage of mass production in this project.

  21. Backup

  22. Command lost (DCM to FEM) • Timing issue when do 8b10b encoder • Original structure 8b10b encoder Controller + Serializer ERROR command DCM to FEM Command FIFO 0101001100 Idle(K28.5) Trig func control Mode control control status

  23. Fix Command lost (DCM to FEM) • New version DCM to FEM CMD FIFO CMD / idle Selector 32b to 8b FIFO 8b10b encoder CMD Serializer 0101001100 Mode select with command for DCM Trig mode func FLT pulse signal

  24. CMAD Control (1)

  25. CMAD Control (2)

  26. CMAD Control (3)

  27. CMAD Control (4)

  28. CMAD Control(5)

  29. DCM ID(10) ChID(4) FEMID(6) ChID(4) FEMID(6)

  30. S-Link Header(1) must be defined.

  31. S-Link Header(2) chosen

More Related