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Advanced Data Acquisition System: Digital vs. Analog Architecture Comparison

This project aims to compare data acquisition architectures based on digital FIFO per ADC versus analog FIFO per channel. Using Monte Carlo modeling, data loss for each architecture is estimated. The project also defines the ADC specifications and outlines the new readout system's main features. The step-by-step process of the readout system architecture is detailed, along with simulation results and arbitration logic area estimation.

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Advanced Data Acquisition System: Digital vs. Analog Architecture Comparison

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  1. A New Data Acquisition System based onAsynchronous Technique Yu. Bocharov, A. Gumenyuk, A. Klyuev, A. Simakov 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  2. Objectives • To compare architecturesAnalog FIFO per channel vs. Dig.FIFO per ADC • To estimate a data loss for systems based on architectures compared by a Monte Carlo modeling • To define the ADC specifications 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  3. A New Readout System Architecture Main FeatureDigital FIFO per ADCagainstAnalog FIFO per channel As an example – 2 ADC per 128 AFE channelsOther variants – 1, 4 ADCPD – peak detector 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  4. Step 1 When a hit occurs in a channel PD locks the this channel in and sends EVENT signal to the control unit 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  5. Step 2 The control unit writes a channel numberand a time stamp into a Dual-port Memory/FIFO. Any type of arbiter may be used to prevent conflicts of writing 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  6. Step 3 The High Speed ADC converts the outputs of channels which numbers are stored in FIFO 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  7. Step 4 Converted data conjunctly with a channel number and a time stamp are transmitted to the external memory bus 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  8. Step 5 When the conversion is finished a control unit initializes PD and corresponding MEM content and connects ADC to the next channel or switches it to a shutdown state if FIFO is empty 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  9. Structure of the arbitration logic for analog de-randomizer (2007) 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  10. Simulation of the synthesized arbitration logic 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  11. Arbitration logic Area Estimation (Encounter, Faraday standard cells, UMC 0.18) 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  12. Total of hits per cycle probability (%) for128 (a), 64 (b), 32 (c) channel systemat 5% channel occupancy for Poisson processMean – 6.4, 3.2, 1.6 a b c 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  13. % 1 2 MSPS CBM-XYTER data loss as a function of total ADC-channels throughput at the best (1) and worse (2) – numerical simulation 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  14. Analytical estimation of a data loss for a new readout system λ – Poisson distribution parameter, M – number of channels per ADC, θ – channel occupancy, μ – max number of channels may be A-D converted within one cycle 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  15. % 3 2 1 MSPS Data loss of a new readout system as function of ADC throughput @ 32 (1), 64(2), 128(3) channels per ADC – analytical and numerical 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  16. Figure of merit (FOM) commonly used for ADC characterization Pd– power dissipationENOB – effective number of bitsfs – sampling frequency (ENOB spec) 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

  17. Summary ADC specs @ Pd = 1 mW/channel andENOB = 6.6 bit (100 quantization levels)Max data loss level = 0.01% • CBM-XYTER120 MSPS, 128 mW, FOM < 10.7 pJ - 1 AD/chip60 MSPS, 64 mW, FOM < 10.7 pJ - 2 AD/chip30 MSPS, 32 mW, FOM < 10.7 pJ - 4 AD/chipAdvantage – reduced ADC requirements • New architecture160 MSPS, 128 mW, FOM < 8.0 pJ - 1 AD/chip105 MSPS, 64 mW, FOM < 6.1 pJ - 2 AD/chip75 MSPS, 32 mW, FOM < 4.3 pJ - 4 AD/chipAdvantage – elimination of 512 analog MEM cells 11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008

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