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TDTL Architecture with Fast Error Correction Technique

ICECS 2010. TDTL Architecture with Fast Error Correction Technique. O. Al-Ali, N. Anani , and P. Ponnapalli School of Engineering Manchester Metropolitan University Manchester, UK M. A. Al- Qutayri and S. R. Al- Araji College of Engineering

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TDTL Architecture with Fast Error Correction Technique

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  1. ICECS 2010 TDTL Architecture with Fast Error Correction Technique O. Al-Ali, N. Anani, and P. Ponnapalli School of Engineering Manchester Metropolitan University Manchester, UK M. A. Al-Qutayri and S. R. Al-Araji College of Engineering Khalifa University of Science, Technology and Research Sharjah Campus, UAE

  2. Outline • Introduction • Conventional DTL • Conventional TDTL System • Conventional Adaptive TDTL • Adaptive TDTL Structure Based on Comparison • Simulation Results • Conclusions and Future work

  3. Introduction • Phase Lock Loop Types Analogue Digital

  4. Introduction • Digital Phase Lock Loop Types • Digital PLLs: Classified as uniform and non-uniform • Non-uniform: • ZCDPLL: Zero crossing Digital PLL • CDTL: Conventional Digital Tanlock Loop • Applications • Clock recovery, hard drive synchronization, satellite communications

  5. Conventional Digital Tanlock Loop (CDTL)

  6. Digital Tanlock Loop (DTL)cont. • Phase Detector Characteristics. where

  7. Digital Tanlock Loop (DTL)cont. • Locking Range.

  8. Time Delay Tanlock Loop (TDTL) • Block Diagram

  9. Time Delay Tanlock Loop (TDTL) cont. • Locking Range. Where , is the steady state phase error

  10. Conventional Adaptive TDTL • Block Diagram

  11. Conventional Adaptive TDTL cont. Limitation • The feed forward arm is active all the time and hence burdens the loop whether there is a change in the incoming signal Frequency or not. Solution • Change the Loop filter only when there is a change in the incoming signal Frequency.

  12. Adaptive TDTL Structure Based on Comparison • Block Diagram

  13. Adaptive TDTL Structure Based on Comparison cont. • Frequency estimator block diagram.

  14. Adaptive TDTL Structure Based on Comparison cont. • Controller block diagram.

  15. Simulation Results • FSK Input Signal, (b) FSK Demodulation using Conventional Adaptive DTL, (c) FSK Demodulation using AC-TDTL. (a) (b) (c)

  16. FSK Demodulation using Conventional Adaptive DTL

  17. FSK and Demodulation using AC TDTL

  18. Simulation Results cont. • FSK Input Signal, (b) Phase plane of the conventional Adaptive TDTL (c) Phase plane of the proposed system AC-TDTL. (a) (b) (c)

  19. Conclusion and Future works • The Adaptive TDTL Structure Based on Comparison compares the frequency of the incoming with that of the DCO signal and acts accordingly without burdening the loop flow. • This results in substantial improvement in the acquisition time by more than three times. • The proposed architecture will require some additional circuitry compared to the conventional TDTL in order to implement the adaptation mechanism. However, the additional circuit overhead is considered acceptable in order to achieve the fast acquisition performance as demonstrated by the results. • Future work will include more extensive evaluation of the loop under different conditions such as noise and high dynamic environment.

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