ECE 699 Digital Signal Processing Hardware Implementations Lecture 1

1. ECE 699�Digital Signal Processing Hardware ImplementationsLecture 1 Course Introduction, Fixed-Point Arithmetic (1) 1/21/09

2. Lecture Roadmap Syllabus and Course Objectives Uses of DSP hardware DSP Hardware Design Flow Fixed-Point Representations Unsigned, Signed Representations Addition Multiplication

3. Syllabus and Course Objectives

4. About the Instructor Dr. David Hwang PhD in Electrical Engineering, UCLA 2005 System Architectures and VLSI Implementations of Secure Embedded Systems Worked in industry designing VLSI signal processing algorithms and circuits Research Interests Secure embedded systems Cryptographic hardware and circuits VLSI digital signal processing VLSI systems and circuits

5. Course Objectives At the end of this course you should be able to: Model fixed-point DSP algorithms in Matlab and calculate quantization error Implement fixed-point DSP algorithms in VHDL on FPGA-based platforms Perform high-level optimizations such as pipelining, folding, unrolling, etc. Design efficient DSP blocks such as FIR filters, FFTs, and direct digital frequency synthesizers Use DSP-specific building blocks in Xilinx FPGAs Understand general tradeoffs in DSP implementations between hardware vs. software and FPGAs vs. ASICs This knowledge will come about through lectures, homework, exams, and student presentations

6. Prerequisites: VHDL/FPGA This class assumes proficiency with synthesizable VHDL and the FPGA CAD tools from ECE 545 As a refresher, go to last semester's ECE 545 and run through the hands-on sessions You are expected to be proficient with: Synthesizable VHDL Dataflow vs. behavioral vs. structural VHDL coding styles Advanced VHDL testbenches with I/O Use of generics and generate statements VHDL simulation with Modelsim and/or Aldec Active-HDL FPGA synthesis tools using XST and/or Synplicity, and post-synthesis simulation and analysis Place-and-route tools using Xilinx ISE, post-place and route simulation and timing analysis Xilinx FPGA structures, including Xilinx block RAM vs. distributed RAM, etc.

7. ECE 699 FPGA CAD Tool Flows The above four design flows are all installed on the lab computers in ST2 203 and ST2 265 The two design flows using XST can also be emulated on your laptop or home computer using the techniques shown on the web site: http://mason.gmu.edu/~dhwang/ece699/spring2009/

8. Prerequisites: DSP/Matlab This class assumes basic undergraduate exposure to digital signal processing You can review DSP topics from an undergraduate textbook such as: Proakis and Manolakis, Digital Signal Processing: Principles, Algorithms, and Applications, 3rd or 4th edition Oppenheim, Schafer, and Buck, Discrete-Time Signal Processing, 2nd edition You are expected to have basic knowledge of Sampling theory and A/D conversion Difference equations Discrete-time convolution and correlation Fourier domain, discrete-time Fourier transforms, FFT FIR and IIR filters Z-domain analysis (poles, zeros) Basic probability, expected value, etc. You should also have previous exposure to Matlab/Simulink

9. ECE 699 Matlab/Simulink Tool Flows The following Matlab/Simulink will be used in this class (available in ST2 203, 265) Matlab/Simulink R2007a Matlab signal processing toolbox Simulink signal processing blockset Matlab fixed point toolbox (maybe) Simulink fixed point (maybe) You can get a student version of the most recent Matlab/Simulink (including signal processing toolbox and signal processing blockset) for $99 directly from Matlab http://www.mathworks.com/academia/student_version/

10. Uses of DSP Hardware

11. Why use DSP hardware? With advent of VLSI (very-large-scale-integrated circuits) Digital signal processing replace many analog signal processing functions Digital signal processing advantages over analog signal processing Digital circuits more robust over temperature, process, and time than analog circuits Digital circuits can perform more complex computations than analog circuits Digital signal processing hardware can allow for flexibility and programmability Accuracy in digital systems easily controlled by wordlength of signal

12. Two methods of implementing DSP hardware Digital signal processing can be performed in hardware in one of two methods: Method 1: programmable digital signal processor Similar to a microcontroller in its programmability (i.e. program memory, data memory, etc.) and flexibility Designed specifically to implement DSP functions efficiently (i.e. multiply-accumulate) Program signal processing functionality in C or assembly code, compile, load to program memory Example: Texas Instrument C54x DSP for mobile phones Method 2: custom-designed DSP circuits on FPGAs/ASICs Highest performance achievable for DSP in hardware Must create new design for each new algorithm Design circuit in HDL (FPGAs, ASICs) or full-custom circuit design (ASICs) Example: Broadcom chips for satellite TV, cable modems, Ethernet transceivers, Marvell chip for 802.11b transceiver In this class we will focus on method 2

13. Current Examples of DSP Hardware Example 1: GSM mobile phone chipset Example 2: xDSL modem Example 3: 802.11b wireless LAN chipset Example 4: 1GBASE-T Ethernet Transceiver Example 5: DVB-H Receiver Exampe 6: Software-Defined Radio Platform

14. Examples:Programmable Digital Signal Processor(Method 1)

15. Example 1: GSM Mobile Phone Handset Texas Instruments TCS2200 GSM/GPRS mobile handset Used for voice and data on GSM networks such as AT&T/Cingular and T-Mobile Digital baseband performs digital signal processing of voice and data streams Heart of digital baseband consists of two processing cores: C54x DSP and ARM7 core C54x DSP is a fixed-point programmable digital signal processor ARM7 core is a 32-bit embedded RISC processor

16. Example 1 cont'd: Inside the TI C54x processor datapath

17. Examples:Custom-Designed DSP circuits on FPGAs and ASICs(Method 2)

18. Example 2: xDSL Modem Transceiver Broadcom VDSL modem transceiver DSP hardware components in red? structures similar to those to be designed in this course

19. Example 3: 802.11b Wireless LAN Chipset Marvell 802.11b chipset composed of 802.11 RF transceiver and Baseband Processor (BBP) Baseband processor implements digital signal processing functions

20. Example 3 cont'd: Baseband Processor DSP hardware components in red? structures similar to those to be designed in this course

21. Example 4: Gigabit Ethernet Transceiver Broadcom 1GBASE-T Gigabit Ethernet Transceiver Used in desktop and notebook computers Pervasive use of digital filters for various signal conditioning, filtering, cancellation

22. Example 5: DVB-H DVB-H is the standard for mobile digital TV Launched in Europe, parts of the U.S. Uses OFDM (orthgonal frequency division multiplexing) FFT as a core processing engine

23. Example 6: Software-Defined Radio Pentek software defined radio Software defined radio is a radio which components implemented in hardware (coding, demodulation, etc.) are implemented in software. Very flexible and SDRs can be programmed via to implement many communication algorithms. Current SDR platforms are often implemented in FPGA boards or boards with FPGAs and DSPs on them; still partially in hardware. The future goal is to have analog and RF components and then only powerful microprocessors or DSPs to perform communication functionality (example: www.vanu.com)

24. DSP Design Flow

25. Typical DSP System Design Flow

26. Number Representations

27. Binary Positional number system Two symbols, B = { 0, 1 } Easily implemented using switches Easy to implement in electronic circuitry Algebra invented by George Boole (1815-1864) allows easy manipulation of symbols Binary Number System

28. Modern Arithmetic and Number Systems Modern number systems used in digital arithmetic can be broadly classified as: Fixed-point number representation systems Integers I = {-N, �., N} Rational numbers of the form x = a/2f, a is an integer, f is a positive integer Floating-point number representation systems x * bE, where x is a rational number, b the integer base, and E the exponent Note that all digital numbers are eventually coded in bits {0,1} on a computer Focus on fixed-point number representation systems in this course Primarily use binary unsigned and two's complement

29. Fixed-Point Number Representations:Unsigned Binary

30. Fixed-Point Number Representations Fixed-point number representations can be generally categorized as unsigned or signed Unsigned numbers represent non-negative numbers; signed numbers represent negative and positive numbers We focus on: Unsigned binary Two's complement (signed)

31. Unsigned Binary Representation K integer bits, L fractional bits More integer bits, the larger the maximum representable value Larger the L, the greater the precision Notation UN.L U indicates unsigned N = number of total bits (i.e. K + L) L = number of fractional bits This is the notation used in fixed-point Matlab In hardware, there is no such thing as a "binary point" (i.e. decimal point) Designer must keep tack of appropriate binary point

32. Unsigned Binary Examples U7.0 example : 0100101. = (37)10 U5.3 example : 01.001 = (9/8 = 1.125)10 U5.4 example : 0.1001 = (9/16 = 0.5625)10 U5.7 example : .[00]01001 = (9/128 = 0.0703125)10

33. Maximum Representable Range UN.L unsigned number has decimal range: Minimum: 0 Maximum: 2K-2-L = 2N-1 / 2L which is obtained when xi=1 for all i Exact representable range: 0 = X = 2K-2-L Rule of thumb: range of number X in UN.L notation 0 = X < 2K The number of integer bits K largely determines the maximum representable range

34. Unsigned Binary Maximum Representable Range Examples U7.0 ? rule of thumb: 0 = X < 128 (K=7) min: 0000000 = (0)10 max: 1111111 = (27-1 / 20 = 127)10 U5.3 ? rule of thumb: 0 = X < 4 (K=2) min: 00.000 = (0)10 max: 11.111 = 25-1 / 23 = 3.875 U5.4 ? rule of thumb: 0 = X < 2 (K=1) min: 0.0000 = (0)10 max: 1.1111 = 25-1 / 24 = 1.9375 U5.7 ? rule of thumb: 0 = X < 0.25 (K=-2) min: .[00]00000 = (0)10 max: .[00]11111 = 25-1 / 27 = 0.2421875

35. Fixed-Point Number Representations:Two's Complement

36. Signed Representations There are several ways of implementing fixed-radix, signed representations 1) Signed-Magnitude redundant 2) Biased (non-redundant) non-redundant 3) Complement A) Radix Complement (r=2 ? "two's complement) non-redundant B) Digit Complement or Diminished-Radix Complement (r=2 ? "one's complement" redundant Redundant ? use two representations for the same number, have symmetric range Non-redundant ? each representation is a different number, have assymetric range

38. Complement Representations with Radix 2

39. One's Complement Representation

40. Useful Dependencies

41. One's Complement Transformation

42. One's Complement Representation of Signed Numbers

43. One's Complement Mapping

44. 4-bit One's Complement Representation

45. One's Complement in a nutshell Values starting with '0' are non-negative Values starting with '1' are negative To obtain value, invert all bits i.e. 1110 = -0001 = (-1)10 i.e. 1100 = -0011 = (-3)10 The decimal value 0 is redundant, can be represented as: Example (K=4, L=0): 0000 = (0)10 or 1111 = (-0)10 For a one's complement value X with K integer bits and L fractional bits (and N total bits), the maximum representable range is: Exact representable range: -(2K-1-2-L) = X = 2K-1-2-L Range is symmetric

46. Two's Complement Representation

47. Two's Complement Transformation (1)

48. Two's Complement Transformation(2)

49. Two's Complement Representation of Signed Numbers

50. Two's Complement Representation of Signed Integers

51. 4-bit Two's Complement Representation

52. One's Complement versus Two's Complement Two's complement is easier to implement than one's complement in hardware (addition, subtraction, multiplication), even though it is not symmetric In the majority of digital systems, representation is either in: Two's complement ? when dealing with positive and negative numbers Unsigned binary ? when dealing with non-negative numbers only

53. Two's Complement Notation K integer bits, L fractional bits More integer bits, the larger the maximum representable value Larger the L, the greater the precision Notation SN.L S indicates signed two's complement N = number of total bits (i.e. K + L) L = number of fractional bits This is the notation used in fixed-point Matlab In hardware, there is no such thing as a "binary point" (i.e. decimal point) Designer must keep tack of appropriate binary point

54. Two's Complement Examples S7.0 examples: positive: 0100101. = (37)10 negative: 1001011. = - 0110101. = (-53)10 S5.3 examples: positive: 01.001 = (9/8 = 1.125)10 negative: 11.000 = - 01.000 = (-1.0)10 S5.4 examples: positive: 0.1001 = (9/16 = 0.5625)10 negative: 1.1000 = - 0.1000 = (-0.5)10 S5.7 example : positive: .[00]01001 = (9/128 = 0.0703125)10 negative: .[11]11000 = - .[00]01000 = (-8/128 = -0.625)

55. Maximum Representable Range SN.M unsigned number has decimal range: Minimum: -2K-1 = -2(N-L-1) which is obtained when xi=1 for i=K-1 and xi=0 otherwise Minimum value is the largest negative value Maximum: 2K-1-2-L = 2N-1-1 / 2L which is obtained when xi=0 for i=K-1 and xi=1 otherwise Maximum value is the largest positive value Exact representable range: -2K-1 = X = 2K-1-2-L Range is assymetric Rule of thumb: range of number X in SN.L notation -2-K-1 = X < 2K-1 K = N � L, the number of integer bits The number of integer bits K largely determines the maximum representable range

56. Two's Complement Maximum Representable Range Examples S7.0 ? Rule of thumb -64 = X < 64 (K = 7) minimum: 1000000. = - 1000000 = (-64)10 maximum: 0111111. = (63)10 S5.3 ? Rule of thumb -2 = X < 2 (K= 2) minimum: 10.000 = - 10.000 = (- 2.0)10 maximum: 01.111 = - 01.111 = (1.875)10 S5.4 ? Rule of thumb -1 = X < 1 (K= 1) minimum : 1.0000 = - 1.0000 = (-1.0)10 maximum: 0.1111 = (0.9375)10 S5.7 ? Rule of thumb -0.125 = X < 0.125 (K= -2) minimum: .[11]10000 = - .[00]10000 = (-16/128 = -0.125)10 maximum: .[00]01111 = (15/128 = 0.1171875)10

57. Two's Complement in a nutshell Values starting with '0' are non-negative Values starting with '1' are negative To obtain decimal value, invert all bits, add LSB, mod by 2K Example S4.0: i.e. 1110 = -(0001 + 0001) mod 24 = -0010 = (-2)10 Example S4.2: i.e. 11.00 = -(00.11 + 00.01) mod 22= (-01.00) = (-1)10 The decimal value 0 is not redundant Can only be represented by all zeros, i.e. 0000 For a two's complement number SN.L (where K=N-L) Exact representable range: -2K-1 = X = 2K-1-2-L Range is asymmetric

58. Summary In this course we will primarily use unsigned binary and two's complement representations Unsigned Binary UN.L (K = N-L) Two's Complement SN.L (K=N-L)

59. Unsigned versus Signed (N=4, L=0 ? K=4)

60. VHDL Number Representations

61. A Word on Notation in VHDL In VHDL, we use std_logic_vector(N-1 downto 0) to represent a UN.L or SN.L number So x(N-1) in VHDL refers to the digit xK-1 and x(0) in VHDL refers to the digit x-L The VHDL designer must keep track of the binary point (via comments usually)

62. VHDL arithmetic operations Synthesizable arithmetic operations: Addition: + Subtraction: - Comparisons: >, >=, <, <= Multiplication: * Division by a power of 2: /2**6(equivalent to right shift)

63. VHDL keywords for arithmetic Unsigned binary in VHDL Data type: unsigned Using std_logic_unsigned will allow you to treat std_logic_vectors as unsigned data types in arithmetic functions Two's complement in VHDL Data type: signed Using std_logic_signed will allow you to treat std_logic_vectors as signed data types in arithmetic functions

64. IEEE Packages for Arithmetic std_logic_1164 Official IEEE standard Defines std_logic and std_logic_vector example: std_logic_vector(7 downto 0) These are for logic operations (AND, OR) not for arithmetic operations (+, *) std_logic_arith Not official IEEE standard (created by Synopsys) Defines unsigned and signed data types, example: unsigned(7 downto 0) These are for arithmetic (+,*) not for logic (AND, OR) std_logic_unsigned Not official IEEE standard (created by Synopsys) Including this library tells compiler to treat std_logic_vector like unsigned type in certain cases For example, can perform addition on std_logic_vector Used as a helper to avoid explicit conversion functions std_logic_signed Not official IEEE standard (created by Synopsys) Same functionality as std_logic_unsigned except tells compiler to treat std_logic_vector like signed type in certain cases Do not use both std_logic_unsigned and std_logic_signed at the same time! If need to do both signed and unsigned arithmetic in same entity, do not use std_logic_unsigned or std_logic_signed packages ? do all conversions explicitly

65. Library inclusion When dealing with unsigned arithmetic use: LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ? needed for using unsigned data type USE ieee.std_logic_unsigned.all; When dealing with signed arithmetic use: LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ? need for using signed data type USE ieee.std_logic_signed.all; When dealing with both unsigned and signed arithmetic use: LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ? Then do all type conversions explicitly

66. History: std_logic_arith versus numeric_std History Package std_logic_arith created by Synopsys as a stop-gap measure Eventually, the IEEE created their own official �version� of std_logic_arith called numeric_std numeric_std Official IEEE standard Defines unsigned and signed These are for arithmetic (+,*) not for logic (AND, OR) example: unsigned(7 downto 0) Use either numeric_std or std_logic_arith, not both! When dealing with unsigned and/or signed types using numeric_std, use: LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; Since different CAD vendors may implement std_logic_arith differently, you can use numeric_std to be safe However � many legacy designs and companies use std_logic_arith in combination with std_logic_unsigned or std_logic_signed Examples in class and in exams will use std_logic_arith with std_logic_unsigned/signed, and not use numeric_std If you use numeric_std, make sure to declare it properly so all code compiles

67. Example: std_logic_arith versus numeric_std

68. Conversion functions

69. More information? Go to: http://dz.ee.ethz.ch/support/ic/vhdl/vhdlsources.en.html Download std_logic_arith.vhd std_logic_unsigned.vhd std_logic_signed.vhd numeric_std �and compare them

70. Unsigned and Signed Numbers VHDL treats all unsigned and signed numbers as integer values (i.e. N=K and L=0) The VHDL coder must keep track of where the exact binary point is N-bit unsigned number: unsigned(N-1 downto 0) Has a decimal range of 0 to 2N-1 Example: unsigned(7 downto 0) has a decimal range 0 to 255 N-bit signed number (two�s complement) number: signed(N-1 downto 0) Has a decimal range of -2N-1 to 2N-1-1 Asymmetric range due to non-redundant representation of 0 Example: signed(7 downto 0) has a decimal range -128 to 127 MSB indicates sign �0� in MSB means non-negative (0 or positive) �1� in MSB means negative Sign extension does not affect value Example: 010 and 00010 both represent decimal 2 Example: 110 and 11110 both represent decimal -2

71. Sign Extension and Shifting

72. Sign Extension Convert a UN.L number into a UN'.L' number while maintaining same value (requires L' >= L and N' >= N): For the MSBs, pad with '0' For the LSBs, fill with '0' Example: convert U6.2 to U9.3 while maintaining value U6.2 : 0100.01 = (4.25)10 U9.3 :000100.010 = (4.25)10 Convert a SN.L number into a SN'.L' number while maintaining same value (requires L' >= L and N' >= N): For the MSBs, sign extend current MSB For the LSBs, fill with '0' Example: convert S6.2 to S9.3 while maintaining value S6.2 : 1100.01 = -(0011.11) =(-3.75)10 S9.3 :111100.010 = -(000011.110)=(-3.75)10

73. Shifting Left/Right Multiplying a UN.L value by two requires a U(N+1).L output Shift all bits to left by one, fill '0' in new LSB Example: U6.2 multiply by 2 U6.2 : 0100.01 = (4.25)10 U6.2 x 2: 01000.10 = (8.50)10 = U7.2 Dividing a UN.L value by two requires U(N+1).(L+1) output without losing information Shift all bits right by one, fill '0' in new MSB Example: U6.2 divided by 2 U6.2 : 0100.01 = (4.25)10 U6.2 / 2: 0010.001 = (2.125)10 = U7.3 Multiplying a SN.L value by two requires S(N+1).L output Shift all bits to left by one, fill '0' in new LSB Example: S6.2 multiply by 2 S6.2 : 1100.01 =(-3.75)10 S6.2 x 2: 11000.10 = (-7.5)10 = S7.2 Divide a UN.L value by two requires S(N+1).(L+1) output without losing information Shift all bits right by one, sign-extend current MSB Example: S6.2 divided by 2 S6.2 : 1100.01 =(-3.75)10 S6.2 x 2: 1110.001 = (-1.875)10 = S7.3

74. Shifting Left/Right Without Word Growth To multiply by 2 or divide by 2 without wordlength growth, you can simply "move the binary point" Requires no hardware. Designer keeps track of where binary point is located. Consider a UN.L value to be a: UN.(L-1) value to multiply by 2 UN.(L+1) value to divide by 2 Example: U6.2 : 0100.01 = (4.25)10 U6.2 x 2: 01000.1 = (8.50)10 = U6.3 U6.2 / 2: 010.001 = (2.125)10 = U6.5 Consider a SN.L value to be a: SN.(L-1) value to multiply by 2 SN.(L+1) value to divide by 2 Example: S6.2 : 1100.01 = (-3.75)10 S6.2 x 2: 11000.1 = (-7.50)10 = S6.3 U6.2 / 2: 110.001 = (-1.875)10 = S6.5 Multiply or divide by two is truly "free" but must keep track of binary point!

75. Number Representations and Addition

76. Addition: General Comments In general, to add two numbers: Line up binary points For unsigned addition Y = X1 + X2 X1 = UN1.L1 , X2 = UN2.L2 If K2>K1 add padding '0's to MSB of X1 until K1=K2; do vice-versa if K1>K2 If L2>L1 add padding '0's to LSB of X1 until L1=L2; do vice-versa if L1>L2 Now both operands have the same wordlength, so add the two numbers For signed addition Y = X1 + X2 X1 = SN1.L1 , X2 = SN2.L2 If K2>K1 sign-extend MSB of X1 until K1=K2; do vice-versa if K1>K2 If L2>L1 add padding '0's to LSB of X1 until L1=L2; do vice-versa if L1>L2 Now both operands have the same wordlength, so add the two numbers We sign-extend/pad for hand-calculation and notational purposes The actual hardware implementation may take advantage of the fact that some bits are always zero or always the same via sign-extension! Later, we will see how to calculate the exact value of N and L for the summation Y when the input N's and L's are different.

77. Half-adder

78. Half-adderAlternative implementations (1)

79. Full-adder

80. Full-adder Alternative implementations (1)

81. Full-adder Alternative implementations (2)

82. Full-adder Alternative implementations (4)

83. Adding two N-bit numbers In general adding two N bit numbers requires an N+1 bit result to prevent overflow. If only have an N-bit result, could have overflow. This is true for both unsigned and signed addition.

84. Unsigned Addition vs. Signed Addition Hardware for unsigned adder is the same as for signed adder (except overflow detection)!

85. Out of Range/Overflow Detection

86. Overflow for Signed Numbers

87. Two's Complement Addition and Overflow

88. Adder with Overflow Detection If used as unsigned adder, cout represents overflow flag If used as signed adder, Overflow represents overflow flag

89. VHDL and Overflow

90. Dealing with Overflow in Addition When adding two N bit numbers, 3 options to deal with overflow: 1) ignore overflow. Keep an N bit output result. If overflow occurs, you just live with the consequences. 2) prevent overflow. Keep an N+1 bit output result so overflow is not possible. 3) detect overflow. Keep an N bit output result. Also build circuitry to detect overflow (detection for unsigned addition is different than from signed addition).

91. Unsigned VHDL

92. Adding Unsigned Binary Numbers: Ignoring Overflow OPTION 1: Ignoring overflow, adding a UN.L binary unsigned number to a UN.L binary unsigned number results in a UN.L number Example: 1111.01 + 1110.10 = 11101.11

93. Adding Unsigned Binary Numbers: Ignoring Overflow in VHDL

94. Adding Unsigned Binary Numbers: Preventing or Detecting Overflow OPTION 2: To prevent overflow, adding a UN.L binary unsigned number to a UN.L binary unsigned number results in a U(N+1).L number Example: 1000.00 + 1000.00 = 10000.00

95. Adding Unsigned Binary Numbers: Preventing or Detecting Overflow in VHDL Zero pad input values with '0', then add and ignore (i.e. do not compute) final carryout (cK+1) Example: 00111.01 + 00110.10 = 001101.11

96. Addition of Unsigned Numbers

97. Signed VHDL

98. Adding Two's Complement Numbers: Ignoring Overflow OPTION 1: Ignoring overflow, adding an SN.L two's complement number to an SN.L two's complement number results in an SN.L number (may get overflow) Example: 0111.01 + 1000.00 + 0110.10 = 1001.00 = 01101.11 10001.00

99. Adding Two's Complement Numbers: Ignoring Overflow in VHDL

100. Adding Two's Complement Numbers: Preventing or Detecting Overflow OPTION 2: To avoid overflow, adding an SN.L number to an SN.L two's complement number results in an S(N+1).L number. To compute, sign extend MSB, ignore cK+1 Example: 00111.01 + 00110.10 = 001101.11

101. Adding Two's Complement Numbers: Preventing Overflow in VHDL Sign extend input values, then add and ignore (i.e. do not compute0 final carryout (cK+1) Example: 00111.01 + 00110.10 = 001101.11

102. Addition of Signed Numbers

103. Adding Two's Complement Numbers: Detecting Overflow in VHDL

104. Multiplication Output Range Multiplication: A x B = C Unsigned multiplication UN.L x UN'.L' = U(N+N').(L+L') number U4.3 x U5.4 = U9.7 number Example: Binary: 1.101 x 1.1001 = 10.1000101 Decimal: 1.625 x 1.5625 = 2.5390625 Signed multiplication (two's complement) SN.L x SN'.L' = (N+N').(L+L') number S4.3 x S4.3 = S8.6 number Example: Binary: 1.000 x 1.000 = 01.000000 Decimal: -1 x -1 = 1 Binary: 0.111 x 0.111 = 00.110001 Decimal: 0.875 x 0.875 = 0.765625 Binary: 1.000 x 0.111 = 11.001000 Decimal: -1 x 0.875 = -0.875 NOTE: Only need K+K' integer bits when A and B are their most negative allowable values If A and B can be restricted such that they do not reach most negative allowable values, then only need K+K'-1 integer bits, i.e. output result is S(N+N'-1).(L+L') Save one MSB: this is a useful trick often using in DSP systems to reduce wordlengths!

105. Multiplication Example in VHDL

106. VHDL Code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity multiplier_trunc is port( a : in std_logic_vector(4 downto 0); -- S5.4 b : in std_logic_vector(4 downto 0); -- S5.4 y : out std_logic_vector(4 downto 0)); -- S5.4 end multiplier_trunc; architecture dataflow of multiplier_trunc is signal multout : std_logic_vector(9 downto 0); -- S10.8 begin multout <= a * b; -- S10.8 y <= multout(8 downto 4); -- S5.4 after removing MSB and truncating end dataflow;