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Energy Recycling Circuit for Leakage Power Reduction Hanh-Phuc Le and Jiashu Chen Motivations - Previous Arts VISU Energy Recycling Converter Analysis and Optimizations of the Circuit Proposals Current detection circuit Leakage power reduction estimation Proposals
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Energy Recycling Circuit for Leakage Power Reduction Hanh-Phuc Le and Jiashu Chen Motivations - Previous Arts VISU Energy Recycling Converter Analysis and Optimizations of the Circuit Proposals Current detection circuit Leakage power reduction estimation Proposals Applications and idea of double-recycling Comparison and Conclusions May 8th, 2008
Technology Scaling (α): Vdd Vdd / α but Idd Idd * α and density increases α2 Motivations Surging Power Density … … leads to the need for Power reduction techniques PLeakage : 30%-40% Ptotal Power increase α2
Leakage Power Reduction – Reported Work MTCMOS Dynamic Body Bias Sleep Transistor
De-coupling Capacitor (de-cap) Solutions for Leakage Reduction at De-cap • Zigzag [3-4] • Staking effect • Require more routings and computational efforts. • Savings of 80%-90% K.S. Min (ISSCC 2003) • Charge Sharing [5] • Short 2 virtual rails • Require matched caps • Ideal savings of 50% E. Pakbaznia (2006)
Outlines • Motivations - Previous Arts • VISU Energy Recycling Converter • Analysis and Optimizations of the Circuit • Proposals • Current detection circuit • Energy savings optimization • Leakage power reduction estimation • Applications and idea of double-recycling • Comparison and Conclusions
Variable-Input Step-up (VISU) Converter • Advantages: • Efficiently return energy of the de-cap to Global Vdd. • Suppress residual leakage to be minimum. • No effect on the operation and robustness of the main circuit. • Simple and flexible
Modified Current Detector Y.J. Woo (ISSCC 2008) • Characteristics: • Fast response, accurate • Replicable for PMOS current sense • Simple
Energy Savings - Optimization Saved Energy Available Energy Energy Loss Energy Loss • Performance: • Recycle 59 nJ / 65 nJ available • Effi = 91 % • Fast convergence time: 800ns • Setup: • Decap = 130 nF • L = 2 nH, ESR = 0.2 Ω • 45nm Hi-K CMOS Tech.
Leakage Power Savings Leakage Power Savings versus Idle time Leakage Power Savings versus Idle cycle reflect Activity factor • Characteristics: • Reach to the discharge speed of no de-cap • Possibly being more aggressive for high activity factor
Proposed to Recycle VISU Converter - Conclusion Idea to Recycle the Energy-Recycling VISU Converter Sleep-mode Energy-Recycling VISU Converter
Professor Bora Nikolic Professor Elad Alon Kevin Mullally and Cory Helpdesk for help in simulation tools. Acknowledgements