EE466: VLSI Design. Lecture 02 Non Ideal Effects in MOSFETs. Outline. Junction Capacitances Parasitic capacitances Velocity Saturation Channel length modulation Threshold Voltage Body effect Subthreshold conduction.
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Non Ideal Effects in MOSFETs
Planar junctions 2, 3 and 4 are surrounded by the p+ channel stop implant.
Planar junction 1 is facing the channel while the bottom planar junction 5 is facing the p-type substrate with doping NA.
The junction types will be n+/p, n+/p+, n+/p+ n+/p+ and n+/p.Junction Capacitances
The depletion region charge stored in this area in terms of xd is
A stands for the junction area.
The junction capacitance associated with the depletion region is defined as:
If we differentiate the equation describing Qj with respect to the bias voltage we get Cj.Junction Capacitances
The sidewall zero bias capacitance is Cj0sw and will be different from the previously discussed junction capacitance.
The zero-bias capacitance per unit area can be found as follows:
Where NA(sw) is the sidewall doping density, f0(sw) is the built-in potential of the sidewall junctions.
All sidewalls in a typical diffusion structure have approximately the same junction depth xj.
The zero bias sidewall junction capacitance per unit length is:Junction Capacitances
In order to examine the transient (AC) response of MOSFETs the digital circuits consisting of MOSFETs we have to determine the nature and amount of parasitic capacitances associated with the MOS transistor.
On chip capacitances found on MOS circuits are in general complicated functions of the layout geometries and the manufacturing processes.
Most of these capacitances are not lumped but distributed and their exact calculations would usually require complex three dimensional nonlinear charge-voltage models.
A lumped representation of the capacitance can be used to analyze the dynamic transient behavior of the device.
The capacitances can be classified as oxide related or junction capacitances and we will start the analysis with the oxide related capacitances.MOS Capcitances
If both the source and drain regions have the same width (W), the overlap capacitance becomes: Cgs=CoxWLD and Cgd=CoxWLD.
These overlap capacitances are voltage dependent.
Cgs, Cgd and Cgb are voltage dependent and distributed
They result from the interaction between the gate voltage and the channel charge.
The gate-to-drain capacitance is actually the gate-to-channel capacitance seen between the gate and the drain terminals.
In Cut-off mode the surface is not inverted and there is no conducting channel linking the surface to the source and to the drain.
The gate-to-source and gate-to-drain capacitances are both equal to zero (Cgs=Cgd=0).
The gate-to-substrate capacitance can be approximated by: Cgb=CoxWL
In linear mode the inverted channel extends across the MOSFET between the source and drain. This conducting inversion layer on the surface effectively shields the substrate from the gate electric field making it Cgb=0.MOS Oxide Capacitances
If the MOSFET is operating in saturation mode the inversion layer on the surface does not extend to the drain, but is pinched off.
The gate-to-drain capacitance in therefore zero (Cgd=0).
The source is however still linked to the conducting channel. It shields the gate from the channel leading to Cgb of zero.
The distributed gate-to-channel capacitance as seen between the gate and the source is approximated by: Cgs2/3CoxWL.MOSFET Oxide Capacitance